The USB 2.0 Device IP core is Arasan’s latest development that enables designers in the PC, mobile, consumer and communication ma…
- USB
The USB 2.0 Device IP core is Arasan’s latest development that enables designers in the PC, mobile, consumer and communication ma…
Mature controller solution for OTG and Device applications The USB 2.0 Controller IP products have been available since 1999, are…
USB-C 3.1/DP TX PHY in GF (22nm)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
USB-C 3.1 DP/TX PHY ebdaux in TSMC (N5, N3E)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
USB 3.1 PHY (10G/5G) in GF (22nm)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
USB-C 3.1 SS/SSP PHY in Type-C in TSMC (16nm, 12nm, N7, N6, N5, N5A)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
USB 3.1 PHY (10G/5G) inTSMC (16nm, 12nm, N7, N6, N5,N3E)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
USB 3.1 PHY (10G/5G) in Samsung (14nm, 11nm, 10nm, 8nm, SF5, SF5A, SF4E)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
USB-C 3.1/DP TX PHY in Samsung (14nm, 11nm, 5nm)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
USB-C 3.1/DP TX PHY in TSMC (16nm, 12nm, N7, N6)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
The USB 2.0 OTG IP Core is compliant with the OTG Supplement Rev.
USB 3.1/DisplayPort 1.3 Controller IP Solutions
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
USB 3.1/DisplayPort 1.4 IP Subsystem Solution
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
The USB 3.0 PHY is a , mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into …
Dual-Role Device Controller for USB 3.1
Mature solutions featuring xHCI Host, Device, and Dual-Role Certified for compliance with USB 3.1 Specification v1.0, and xHCI Sp…
USB 2.0 On-The-Go IP Core, Compliance Certified
A ‘Dual-Role’ USB 2.0 On-The-Go IP Core that operates as both an USB 2.0 peripheral or as an USB 2.0 OTG host in a point-to-point…
USB 2.0 Hi-Speed OTG Controller version 4 with Active Clock Gating to save active power
The vendor provides designers with silicon-proven, configurable USB 2.0 Controllers that are compliant with the USB-Implementers …
The vendor provides designers with silicon-proven, configurable USB 2.0 Controllers that are compliant with the USB-Implementers …
USB 2.0 Device Controller version 4 with Active Clock Gating to save active power
The vendor provides designers with silicon-proven, configurable USB 2.0 Controllers that are compliant with the USB-Implementers …