Single Port SRAM Compiler IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process high density, Low Power mini Single Port SRAM.
- SRAM
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Single Port SRAM Compiler IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process high density, Low Power mini Single Port SRAM.
One Port Register File Compiler IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process synchronous high density Single Port Register File SRAM memory compiler.
ROM Compiler IP, UMC 0.162um eHV process
UMC 0.162um eHV process synchronous 1P2M Metal ROM memory compiler.
ROM Compiler IP, UMC 0.153um MS process
UMC 153nm Mixed-Mode/Logic process synchronous Via1 ROM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.153um MS process
UMC 153nm Mixed-Mode/Logic process synchronous high density Dual Port SRAM memory compiler.
SRAM/ROM Controller IP, SRAM/ROM Controller, Soft IP
Static memory controller with AXI interface.
SD host controller wih ahb interface, compliant with the SD Host Controller Standard Specification Version 3.00.
PCIe Controller IP, PCIe Gen-2 with the AXI interface, x4 Lanes, Soft IP
PCIe Gen2 x4 Lane Endpoint Controller.
Memory Controller IP, NAND Flash memory Host controller, Soft IP
NAND flash host controller with AHB interface, it supports SLC and MLC NAND flash.
AXI system Peripheral IP, AXI/APB host bridge, Soft IP
AXI/APB host bridge controller.
SATA Controller IP, SATA Gen-3, Soft IP
SATA Device Controller.
AXI Bus Controller IP, Bus Controller, Soft IP
Register Slice Controller with AXI bus interface.
PCIe Controller IP, PCIe Gen-2 with the AHB interface, x1 Lanes, Soft IP
PCI Express Gen 2 Endpoint Controller.
Memory Controller IP, Memory Stick controller, Soft IP
Memory Stick host controller with AHB Bus.
AHB system Peripheral IP, SRAM/ROM Controller, Soft IP
Embedded synchronous Single Port SRAM/ROM memory controller with up to two AHB slave ports.
AHB system Peripheral IP, External Bus controller, Soft IP
External Bus Interface Controller.
Specialty Analog ESD IO IP, UMC 0.153um LL process
UMC 0.153um Mixed-Mode/Logic process 3.3V Analog ESD IO Cell Library.
Specialty OSC IO IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process 1.8V device high frequency crystal osc IO Library.
Specialty Analog ESD IO IP, UMC 0.153um LL process
UMC 0.153um Mixed-Mode/Logic process 3.3V Analog ESD IO Cell Library.
Specialty OSC IO IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process 1.8V device low frequency crystal osc IO Library.