Mature IPs expand from 2D graphics to video processing and AI preprocessing
- GPU
- Mass Production
- Now
- OpenWF, DirectFBGDI/DirectD…
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Mature IPs expand from 2D graphics to video processing and AI preprocessing
3D GPU series has higher power-efficiency and cost effectiveness in 3D improved performance for 3D graphics rendering and computing.
Highly scalable IP cores to deliver exceptional acceleration
Ultral-small size: 0.033mm2; High performance, low EMI TX driver design
IP
EDP_RX consists of electrical sub-blocks of main-link and AUX channel of PHY for eDP RX.
eDP (Embedded Displayport) receiver Link/PCS IP core is compliant with eDP 1.4a/DP 1.3 specification.
SMIC 0.16um 1.8V<->3.3V level shifter,1.8v/3.3v operating voltage
SMIC 0.16um 1.8V3.3V Level Shfiter Library
SMIC 0.16um Isolation Cell Library,1.8v operating voltage
SMIC 0.16um Isolation Cell Library
SMIC 0.16um 3.3V Standard Cell Library,1.8v operating voltage
SMIC 0.16um 3.3V Standard Cell Library
SMIC 0.16um 9 track Standard Cell Library,1.8v operating voltage
SMIC 0.16um 9T High-Density Standard Cell Library
IP
IP
LVDS 10 bits dual port transmitter
IP
CSMC 0.18um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
VeriSilicon CSMC 0.18um High-Speed Synchronous Memory Compiler optimized for CSMC TECHNOLOGIES CORPORATION Fab2 0.18um MS/RF proc…
VeriSilicon CSMC 0.16um High-Speed Synchronous Memory Compiler optimized for CSMC TECHNOLOGIES CORPORATION Fab2 0.16um MS/RF proc…
CSMC 0.13umLP Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
VeriSilicon CSMC 0.13um Low Power(LP) Process Synchronous Memory Compiler optimized for CSMC Technologies Corporation 0.13um 1P8M…
CSMC 0.13um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
VeriSilicon CSMC 0.13um High-Speed Synchronous Memory Compiler optimized for CSMC TECHNOLOGIES CORPORATION 0.13um 1P8M Mix Proces…
SATA HOST 3 ON KINTEX 7 Ultrascale
The LDS SATA 3 HOST XK7U IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 Ultrascale sp…
VeriSilicon GSMC 0.25um High-Speed Synchronous Memory Compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC)…