UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT
- UMC
- 40nm
- LP
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UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT
UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating
UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating
UMC 40nm LP Logic Process Ultra High Speed One-Port Register File_x005F_x000D_
UMC 40nm LP Logic Process Ultra High Speed One-Port Register File
UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell
UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell
UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell
UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell
UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell
UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery
UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT
UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT
UMC 55nm ULP process PG-One Port Register File for periphery HVT
UMC 55nm ULP process PG-One Port Register File for periphery HVT
UMC 55nm ULP process ROM compiler with HVT peripheral
UMC 55nm ULP process ROM compiler with HVT peripheral
UMC 55nm ULP Low-K process One Port Register File for periphery HVT
UMC 55nm ULP Low-K process One Port Register File for periphery HVT
UMC 55nm LP process with PG Dual port SRAM compiler
UMC 55nm LP process with PG Dual port SRAM compiler
UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler.
UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler.
55ULP-SST 1P-RF with forward biased and UHVT periphery
55ULP-SST 1P-RF with forward biased and UHVT periphery
55ULP-SST 1P-RF with forward biased and HVT periphery
55ULP-SST 1P-RF with forward biased and HVT periphery
UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias
UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery h…
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery h…