eSPI LPC Bridge interface is full-featured, easy-to-use, synthesizable design, compatible with Standard LPC Interface specificati…
- LPC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
eSPI LPC Bridge interface is full-featured, easy-to-use, synthesizable design, compatible with Standard LPC Interface specificati…
eSPI controlller is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of standard eSPI specific…
The eMMC Host IIP core supports the SD Host Controller Specification version 6.0 and compatible with the JESD84-B51 Specification.
eMMC DEVICE interface provides full support for the eMMC DEVICE synchronous serial interface, compatible with JESD84-B51 specific…
eDP Transmitter core is compliant with standard eDP 1.4b specification.
eDP Receiver core is compliant with standard eDP 1.4b specification.
eCPRI Controller interface provides full support for the two-wire eCPRI Controller synchronous serial interface, compatible with …
DSC ENCODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2/1.2a.
DSC DECODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2/1.2a.
Display Port Transmitter core is compliant with Display Port version 2.0 specification.
Display Port Receiver core is compliant with Display Port version 2.0 specification.
DMA Controller with TileLink IIP
DMA Controller with TileLink interface is full featured, easy-to-use, synthesizable design that can be used with TileLink based s…
DMA Controller with OCP interface is full featured, easy-to-use, synthesizable design that can be used with OCP based systems as …
DMA Controller with AXI interface is full featured, easy-to-use, synthesizable design that can be used with AXI based systems as …
DMA Controller with AHB interface is full featured, easy-to-use, synthesizable design that can be used with AHB based systems as …
DFI LPDDR5 is full-featured, easy-to-use, synthesizable design, compatible with LPDDR5 JESD209-5 specification and DFI-version 5.…
IEEE 1149.7 DTS ADAPTER is full-featured, easy-to-use, synthesizable design, compatible with IEEE 1149.7 Compliant.
IEEE 1149.7 COMPACT TAP is full-featured, easy-to-use, synthesizable design, compatible with IEEE 1149.7 Compliant.
CAN CONTROLLER interface provides full support for the two-wire CAN CONTROLLER synchronous serial interface, compatible with CAN …
AVSBUS Slave interface provides full support for the two-wire/ three-wire AVSBUS Slave synchronous serial interface, compatible w…