Verification IP for UCIe
Accelerated confidence in simulation-based verification of RTL designs with Universal Chiplet Interconnect Express (UCIe) interfa…
Overview
Accelerated confidence in simulation-based verification of RTL designs with Universal Chiplet Interconnect Express (UCIe) interfaces
Avery UCIe VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates constrained random traffic gener ation, robust D2D and LogPHY layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debug ging, and performance analysis metrics. PCIe/CXL VIP supports FDI/RDI adapters for complete stack verification. With the advanced capabilities of Avery VIP, engineers can work more efficiently, develop more complex tests, and work on more complex topologies, such as bifurcation. Avery compliance test suites offer effective core-through-chip-level tests, including those used in compliance workshops as well as extended tests developed by Avery to cover the specifica tion features.
Specifications
|
Protocol Family |
Standard Organization |
Sub Protocol |
Models |
|---|---|---|---|
|
UCIe |
Universal Chiplet Interconnect Express (UCIe) |
UCIe 1.0 |
Key features
- Supports latest PCIe Gen5/6 and CXL 2.0/3.0
- Device and retimer supported
- Multiple stacks / multiple protocols
- Raw flit, CXL68B enhanced flit, standard and latency-opti mized 256B flit
- ARB/MUX
- CRC retry
- Link state management
- Parameter negotiation
- Power management link states
- LogPHY supported features
- Link training
- Scrambling/descrambling
- Sideband training transfers
- Lane repair
- Lane reversal
- Main band/sideband interfaces
- FDI / RDI interfaces
- Unit-level FDI / RDI driver mode BFMs for standalone PHY testing
- RDIBox BFM for simplified direct protocol/D2D only testing
- Directed and randomized flit generation
- UCIe PCIe extended config space
- BFM settings are runtime configurable
- Error injection at multiple levels
- Protocol checkers
- Layered protocol debugging trace files
- Throughput measurement
- Compliance test suite
Block Diagram
Benefits
- Offers effective core-through-chip- level tests
- Enables engineers to work more efficiently,
- Supports development of more complex tests and topologies
- Provides enhanced protocol- aware debugging
- Isolates compliance issues
What’s Included?
- UCIe D2D Adapter
- LogPHY
- RDIBox models
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
Learn more about UCIe IP core
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Frequently asked questions about UCIe IP cores
What is Verification IP for UCIe?
Verification IP for UCIe is a UCIe IP core from Siemens Digital Industries Software listed on Semi IP Hub.
How should engineers evaluate this UCIe?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UCIe IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.