UCIe D2D Adapter

Industry Leading, Silicon Proven, 32 Gbps per pin, backed by a complete portfolio of verification tools, PHY interoperability and integration.

The D2D Adapter for UCIe is a scalable adapter layer between one or more protocol components and the UCIe PHY, which ensures efficient data transfer across the UCIe Link by seamlessly coordinating with the Protocol Layer and Physical Layer. By minimizing logic on the main data path, it delivers a low-latency, optimized pathway for protocol Flits. When handling CXL protocol, the D2D Adapter incorporates ARB/MUX functionality to support multiple simultaneous protocols. For scenarios where the Raw BER exceeds 1e-27, it implements the CRC and Retry scheme defined in the UCIe Specification, ensuring reliable data transport for PCIe, CXL, or other protocols including Streaming protocols.

Additionally, the D2D Adapter manages critical functions such as higher-level Link state machine coordination, parameter exchanges with remote Link partners for protocol options, and power management synchronization when supported. The IP Core is silicon and PHY agnostic implementation of UCIe D2D Adapter following the v2.0 standard, targeting ASIC applications. The IP core is thoroughly tested in System Verilog random regression environment.

The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested and integrated with a leading UCIe PHY provider.

The Die to Die Adapter IP interfaces to the UCIe Serdes with the Raw Die to Die Interface (RDI) and to the Protocol Layer with the Flit-Aware Die to Die Interface (FDI). The IP is highly customizable and contains blocks for CRC / Retry logic as well as Protocol and Stack Multiplexers

• Ultra Low Latency
• CRC and Retry, or Parity Computation
• Multiple Protocols,
• Multiple Stacks
• Protocol/Stack Arbitration and Multiplexing
• Link State Management
• Protocol and Parameter negotiation
• Silicon Agnostic

• Test Environment: UCIe D2D Adapter IP is Tested against a VIP model in UVM regression for full functional coverage
• Silicon Agnostic: Designed in Verilog and targeting both ASICs and FPGAs
• PHY Integration: PHY Integration support with additional hours or off the shelf PHY integration package for quick and efficient  deployment
• Active Support: All support is actively provided by engineers directly

• The IP Core can be delivered in Source code or Encrypted format.
• The following deliverables will be provided with the IP Core license:
  • Solid documentation, including User Manual, Release Note and Quick Start Guide.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Timing Constraints in Synopsys SDC format.
  • Access to support system and direct support from Chip Interfaces Engineers.
  • Test Report , Synopsys SGDC Files and Synopsys Lint, CDC and Waivers available on request