Vendor: Cadence Design Systems, Inc. Category: UCIe

Simulation VIP for UCIE

Best-in-Class UCIe Verification IP for your IP, SoC, and System-Level Design Testing The Cadence Verification IP (VIP) for Univer…

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Overview

Best-in-Class UCIe Verification IP for your IP, SoC, and System-Level Design Testing

The Cadence Verification IP (VIP) for Universal Chiplet Interconnect Express (UCIe) is designed for easy integration in test benches at the IP, system-on-chip (SoC), and system level. The VIP for UCIe runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce the time spent on environment development and redirect it to cover a larger verification space, accelerate verification closure, and ensure end-product quality.

With a layered architecture and powerful callback mechanism, verification engineers can verify UCIe features at each functional layer (PHY, D2D, Protocol) and create highly targeted designs while taking advantage of the latest design methodologies for random testing to cover a larger verification space. The VIP for UCIe can be used as a standalone stack or layered with PCIe VIP.

Supported specifications: Universal Chiplet Interconnect Express Specification Version 1.1

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

UCIe 2.0
  • Interoperability supported with 2.0 specification through param negotiation-related updates in the D2D adapter and field updates in the Phy layer

Protocol Layer Features
  • Streaming mode
  • PCIe mode
  • Protocol FDI LSMs
  • Pseudo Protocol port - API interface to inject user-defined FLITs in the protocol layer

D2D Adapter Layer Features
  • Link initialization
  • Adapter initialization
  • Parameter exchange with remote link partner
  • FDI bring up
  • Raw (Format 1 streaming) with RDI/FDI Mb data width 128, 256, 512, 1024, 2048, 4096, 8192 bits
  • 68B FLIT (format 2 streaming and PCIe)
  • Standard 256B end header FLIT (format 3 in streaming and PCIe)
  • Standard 256B start header FLIT (format 4 in streaming)
  • Latency optimized 256B FLIT without optional byte (format 5 in streaming)
  • Latency optimized 256B FLIT with optional byte (format 6 in streaming)
  • Decision table for flit format and protocol
  • D2D adapter FDI LSMs
  • D2D adapter RDI SSM
  • Retry in streaming (format 2, 3, 4, 5, 6)
  • D2D parity
  • Pseudo FDI port - API interface to inject user-defined sideband and mainband packets (FLITs) in D2D adapter layer, bypassing FDI
  • Sideband mailbox
  • Multi-stack

PHY Features
  • Package - Standard (16 lanes) and advanced (64 lanes)
  • Sideband transmission
  • Mainband transmission at link speed per lane 4, 8, 12, 16, 24, 32GT/s
  • Sideband data/clock resolution
  • Lane reversal
  • Data lane repair - single and two lane
  • Single and two lane repair with reversal
  • Clock and track lane remapping and repair
  • Valid lane remapping and repair
  • Scrambling and training pattern generation
  • Link initialization and training
  • Transmitter initiated data to clock point training
  • Transmitter initiated data to clock eye width sweep
  • Receiver initiated data to clock point training
  • Valid framing
  • Retrain flow
  • LTSM
  • PHY RDI SSM
  • Free running clock and strobe mode
  • Standard package single module
  • Advanced package single module
  • Advanced package multi-module link and initialization
  • Standard package multi-module
  • Single module width degrade
  • Psuedo RDI port - API interface to inject user-defined sideband and mainband packets in PHY layer (bypassing RDI)
  • Recalibration
  • Redundant lane training
  • Quadrature clocking

Interfaces
  • FDI (FLIT data interface connecting protocol layer with D2D adapter layer)
  • RDI (raw data interface connecting D2D adapter layer with PHY layer)
  • UCIe PHY mainband and sideband 
  • FDI/RDI Mb data width 128, 256, 512, 1024, 2048, 4096, 8192 bits
  • Multi-byte width up to 4 bytes per laneat link/RDI/FDI
  • FDI/RDI Sb data width 8, 16, 32 bits
  • RDI state machine   
  • RDI bring up flow
  • FDI state machine  
  • FDI bring up flow   
  • Rules and description for lp_wake_req/pl_wake_ack handshake   
  • Rules and description for pl_clk_req/lp_clk_ack handshake   
  • Rx_active_req/Sts handshake   
  • Common rules for FDI and RDI   
  • Byte mapping for FDI and RDI
  • State request and status   
  • LinkReset flow 
  • Disable flow
  • Linkerror flow
  • Retrain flow
  • Dynamic clock gating for FDI/RDI
  • FDI PM flow - L1, L2, Abort
  • RDI PM flow - L1, L2, Abort

Sideband Features
  • Packet Types
  • Register Access Packets
  • Messages without Data
  • Messages with data payloads
  • Flow Control and Data Integrity over UCIe sideband Link between dies

Model Capabilities
  • Standalone layer, Partial stack, Full-stack
  • LTSM training bypass
  • Scrambler bypass
  • Configurable number of D2C training attempts and pattern count
  • Debug ports
  • Packet IDs for packet tracking within a layer
  • RDI SHIM
  • Model registers

Monitor Mode
  • PHY link monitor: Monitors UCIe PHY link excluding RDI SSM and RDI
  • PHY 4Path monitor: Monitors complete PHY layer, including UCIe link, RDI SSM, and RDI
  • PHY RDI Monitor: Monitors PHY RDI interface only and performs pin/interface rules-related checks (excluding PHYRDI SSM monitoring)
  • D2D RDI Monitor: Monitors D2DRDI interface only and performs pin/interface rules-related checks (excluding D2D RDISSM monitoring)
  • D2D FDI Monitor: Monitors D2D FDI interface only and performs pin/interface rules-related checks (excluding D2D FDILSM monitoring)
  • PROTO FDI Monitor: Monitors PROTO FDI interface only and performs pin/interface rules-related checks (excluding PROTO FDI LSM monitoring)

Package
  • Standard (16 lanes)
  • Advanced (64 lanes)

Error Injections
  • Modifiable transaction fields through callbacks
  • Discard packets from the transmission through callbacks
  • Sending to LinkError/Disabled/LinkReset/Retrain in streaming mode
  • Sending to LinkReset/Disabled/Retrain/LinkError in PCIe mode

Key features

  • Support testbench language interfaces for SystemVerilog, UVM
  • UVM building blocks
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Packet tracker and Waveform debugger for efficient debugging
  • SystemVerilog coverage model
  • Trace for issue replay

Block Diagram

Simulation VIP for UCIE block diagram

Files

Product Sheet Download

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Specifications

Identity

Part Number
Simulation VIP for UCIE
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Contact Cadence Design Systems, Inc.

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Frequently asked questions about UCIe IP cores

What is Simulation VIP for UCIE?

Simulation VIP for UCIE is a UCIe IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this UCIe?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UCIe IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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