Vendor: Cadence Design Systems, Inc. Category: I2C / I3C

Simulation VIP for SMBus

Incorporating the latest protocol updates, the Cadence® Verification IP (VIP) for SMBus provides a bus functional model (BFM), in…

Verification IP View all specifications

Overview

Incorporating the latest protocol updates, the Cadence® Verification IP (VIP) for SMBus provides a complete bus functional model (BFM), integrated automatic protocol checks and coverage model. The VIP for SMBus is designed for easy integration in testbenches at IP, systems-on-chip (SoC), and system levels, and helps to reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for SMBus runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: SMBus v3.0

Key features

  • SMBus Devices
    • Controller target, or host
  • Packet Error Checking
    • Performs PEC on transmit and receive data on applicable packets
  • Address Resolution Protocol
    • Resolve addresses for devices on the bus
  • Device Timeout
    • Device timeout condition detection
  • Bus Protocol
    • All bus protocols with and without a packet error code
  • Alert Response Address
    • Alert response protocol for device controller capability
  • Clock Generation and Data Arbitration
    • Clock generation using defined clock timings and data arbitration
  • Clock Synchronization Between Two Controllers
    • Clock synchronization when more than one controller drives clock
  • Optional SMBus Signals
    • SMBSUS in suspend-resume mode signal and SMBALERT for (interrupt line for target signal)

Block Diagram

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Simulation VIP for SMBus
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.

Learn more about I2C / I3C IP core

From I2C to I3C: Evolution of Two-Wire Communication in Embedded Systems

The I2C (Inter-Integrated Circuit) Bus invented in 1980 by Philips Semiconductors (NXP Semiconductors today) was a massive step forward in simplifying communications in embedded systems. It is a simple two-wire interface for synchronous, multi-master/multi-slave, single ended serial communication. Fast forward 45 years to today and it is still widely used for attaching low speed peripheral Integrated Circuits (ICs), processors and microcontrollers. But silicon today has changed...

Maximizing the Usability of Your Chip Development: Design with Flexibility for the Future

Early in my career selling chips for Motorola Semiconductor, the ability to spin derivative microcontroller chips for a customer’s specific requirement was relatively straightforward. If the volume looked reasonable, we would tape-out a new chip with a few added features because mask costs and wafers were relatively inexpensive at the larger process nodes. The customer won by getting an MCU tailored to their specific need, and Motorola won by gaining a more committed customer plus another SKU that could be sold to other customers – boosting ROI. With the migration to higher cost FinFET nodes, those times are long gone as the economics no longer work.

MIPI CCI over I3C: Faster Camera Control for SoC Architects

Imagine a camera subsystem that responds in microseconds, consumes less power, and offers a more straightforward route to time-to-market. For SoC architects and IP integration teams, that vision is increasingly possible with MIPI Camera Control Interface (CCI) over I3C.

Frequently asked questions about I2C / I3C IP cores

What is Simulation VIP for SMBus?

Simulation VIP for SMBus is a I2C / I3C IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP