AVSBus v1.4.1 Verification IP

The AVSBus Verification IP provides an effective and efficient way to verify the components interfacing with AVSBus interface of an IP and SOC. The AVSBus VIP is fully compliant to PMBus part III - AVSBus Specification version 1.4.1. The VIP is lightweight with an easy plug-and-play interface, so that there is no hit on the design cycle time.

• Fully compliant with AVSBus Specification as defined in PMBus version v1.4.1 part III and seamlessly integrated with PMBus Specification v1.4.
• Supports topologies with one controller–one target as well as multi-link configurations.
• Supports both 3-wire bidirectional and 2-wire unidirectional AVSBus communication modes.
• Supports AVSBus data format, including numeric values represented using standard two's complement.
• Supports necessary conversions between AVSBus and PMBus data formats.
• Supports target resynchronization via clock-driven recovery sequences.
• Supports detection and handling of communication timeouts.
• Supports generation of alerts by the master on status change indication.
• Supports frame alignment and allows execution of continuous back-to-back command frames.
• Supports user-defined response frame handling for status monitoring.
• Enables clock suspension during idle periods.
• Supports 64-bit structured support for both read and write frame transactions.
• Supports all read and write types, including Write-and-Commit and Write-and-Hold operations.
• Supports generation of transactions with UVM register model.
• Built in Bus Monitor provides extensive protocol checking.
• Supports Dynamic as well as Static Error Injection and detection scenarios.
  • Invalid StartCode pattern injection
  • 3-bit CRC error injection
  • Invalid selector testing
  • Unsupported command type errors
  • Command group violations
  • Invalid command data types
  • Unavailable resource simulation
  • Reserved bit field violation checks
  • Signal validity checks during clock suspension
• On the fly protocol checking using protocol check functions, static and dynamic assertion.
• Built in Coverage analysis.
• Provides a comprehensive user API (callbacks) in Transmitter & Receiver.
• Graphical analyser for all Layers to show transactions for easy debugging.

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
• Unique development methodology to ensure highest level of quality.
• Availability of Compliance & Regression Test Suites
• 24X5 customer support
• Unique and customizable licensing models
• Exhaustive set of assertions and cover points with connectivity example for all the components
• Consistency of interface, installation, operation and documentation across all our VIPs
• Provide complete solution and easy integration in IP and SoC environment. 

• AVSBus Controller/Target BFM/Agent.
• AVSBus Monitor and Scoreboard.
• Testbench Configurations.
• Test Suite (Available in Source Code).
  • Basic and directed protocol tests
  • Random Tests
  • Error Scenario Tests
  • Assertions & Cover Point Tests
• Integration Guide, User Manual and Release Notes