Vendor: SmartDV Technologies Category: I2C / I3C

AVSBus Synthesizable Transactor

AVSBus Synthesizable Transactor provides a smart way to verify the AVSBus component of a SOC or a ASIC in Emulator or FPGA platfo…

Contact Provider Request Datasheet

Overview

AVSBus Synthesizable Transactor provides a smart way to verify the AVSBus component of a SOC or a ASIC in Emulator or FPGA platform.The SmartDV's AVSBus (Adaptive Voltage Scaling) Synthesizable Transactor is fully compliant with standard AVSBus Specification and provides the following features.

Key features

  • Follows AVSBus basic specification as defined in PMBus 1.3.1 Part III Specification
  • Supports data width upto 64 bits
  • Support AVSBus Master and Slave functionality
  • Supports 3-wire ,2-wire AVSBus interface
  • Supports all AVSBus Commands as per specs
  • Supports clock Resynchronization
  • Supports timeout detection and generation
  • Supports following AVSBus topologies
    • Single Master and Single Slave
    • Multiple links
  • Supports insertion of various errors
    • NACK insertion by Slave
    • CRC Error

Block Diagram

AVSBus Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Complete regression suite containing all the LVDS testcases
  • Synthesizable transactors
  • Examples showing how to connect and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation also contains User's Guide and Release notes

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
AVSBus Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about I2C / I3C IP core

From I2C to I3C: Evolution of Two-Wire Communication in Embedded Systems

The I2C (Inter-Integrated Circuit) Bus invented in 1980 by Philips Semiconductors (NXP Semiconductors today) was a massive step forward in simplifying communications in embedded systems. It is a simple two-wire interface for synchronous, multi-master/multi-slave, single ended serial communication. Fast forward 45 years to today and it is still widely used for attaching low speed peripheral Integrated Circuits (ICs), processors and microcontrollers. But silicon today has changed...

Maximizing the Usability of Your Chip Development: Design with Flexibility for the Future

Early in my career selling chips for Motorola Semiconductor, the ability to spin derivative microcontroller chips for a customer’s specific requirement was relatively straightforward. If the volume looked reasonable, we would tape-out a new chip with a few added features because mask costs and wafers were relatively inexpensive at the larger process nodes. The customer won by getting an MCU tailored to their specific need, and Motorola won by gaining a more committed customer plus another SKU that could be sold to other customers – boosting ROI. With the migration to higher cost FinFET nodes, those times are long gone as the economics no longer work.

MIPI CCI over I3C: Faster Camera Control for SoC Architects

Imagine a camera subsystem that responds in microseconds, consumes less power, and offers a more straightforward route to time-to-market. For SoC architects and IP integration teams, that vision is increasingly possible with MIPI Camera Control Interface (CCI) over I3C.

Frequently asked questions about I2C / I3C IP cores

What is AVSBus Synthesizable Transactor?

AVSBus Synthesizable Transactor is a I2C / I3C IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP