MIPI I3C Synthesizable Transactor
MIPI I3C Synthesizable Transactor provides a smart way to verify the MIPI I3C component of a SOC or a ASIC in Emulator or FPGA pl…
Overview
MIPI I3C Synthesizable Transactor provides a smart way to verify the MIPI I3C component of a SOC or a ASIC in Emulator or FPGA platform. MIPI I3C Synthesizable Transactor provides an smart way to verify the MIPI I3C bi-directional two-wire bus. The SmartDV's MIPI I3C Synthesizable Transactor is fully compliant with Specification for I3C version 1.1 and provides the following features.
Key features
- Compliant with MIPI I3C version 1.1 specification
- Supports full MIPI I3C Master and Slave functionality
- Two wire serial interface up to 12.5 MHz using Push-Pull with the following Data rates supported
- Standard speed
- Supports all topologies
- Single master – Single slave
- Single master – Multi slave
- Multi master – Single slave
- Multi master – Multi slave
- Dynamic Addressing while supporting Static Addressing for legacy I2C devices.
- Supports I3C address arbitration.
- Supports Single Data Rate (SDR) messaging.
- Direct CCC
- Broadcast CCC
- Supports High Data Rate (HDR) messaging
- HDR-Dual Data Rate Mode (HDR-DDR)
- HDR-Ternary symbol for Pure bus (HDR-TSP)
- HDR-Ternary symbol Legacy inclusive bus (HDR-TSL)
- In-Band Interrupt support and Hot-Join support
- Legacy I2C Device co-existence on the same Bus instance
- Supports error detection and recovery
- Supports injection of various errors by master
- Broadcast address/ I3C address error
- SDR write data parity error
- Dynamic address parity error
- Illegal CCC error
- HDR command parity and preamble error
- HDR write data parity and preamble error
- HDR CRC and frame error
- Supports injection of various errors by slave
- Broadcast address/ I3C address nack error
- Illegal CCC error
- I2C write data nack error
- SDR read data parity error
- HDR read data preamble and parity error
- HDR read CRC error
Block Diagram
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the MIPI I3C testcases
- Examples showing how to connect various components, and usage of Synthesiable VIP
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
Learn more about I2C / I3C IP core
Maximizing the Usability of Your Chip Development: Design with Flexibility for the Future
MIPI I3C v1.1 - A Conversation with Ken Foust
How to Connect Sensors with I3C
MIPI CCI over I3C: Faster Camera Control for SoC Architects
Arasan I3C PHY - Ternary vs. Non-Ternary
Frequently asked questions about I2C / I3C IP cores
What is MIPI I3C Synthesizable Transactor?
MIPI I3C Synthesizable Transactor is a I2C / I3C IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this I2C / I3C?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.