Vendor: SmartDV Technologies Category: I2C / I3C

SMBus Synthesizable Transactor

SMBus Synthesizable Transactor provides a smart way to verify the SMBus component of a SOC or a ASIC in Emulator or FPGA platform.

Overview

SMBus Synthesizable Transactor provides a smart way to verify the SMBus component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's SMBus Synthesizable Transactor is fully compliant with version of 3.0 SMBus Specification and provides the following features.

Key features

  • Supports SMBus specification version 3.0
  • Supports all SMBus device types: Master, Slave
  • Supports all SMBus command as per the specs
  • Supports programmable clock frequency of operation
  • Supports ARP command generation and response
  • Supports Timeout detection and generation
  • Alert generation and handling
  • Supports bus-accurate timing
  • Supports packet error checking
  • Supports master/slave arbitration and clock synchronization
  • Supports glitch insertion and detection
  • Supports insertion of errors
    • Master aborting in middle of transaction
    • ACK on last read phase by master
    • Master doing ACK on last read access
    • Master continue on NACK after write NACK from slave
    • Random and Periodic clock period stretching by slave
    • Random Write NACK insertion by slave
    • Glitch injection on clock and data at various windows
    • PEC error
    • Timeout error insertion
    • ACK for PEC field by master for read data
    • Wrong ARP address
    • Unsupported command codes
    • Illegal commands lengths
  • Generates and handles glitches generating on both SMBDAT and SMBCLK lines
  • Supports timeouts forcing and handling
  • Support for multiple instantiations to create complex verification environment
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations
  • SMBus Verification IP comes with complete testsuite to test every feature of SMBus specification

Block Diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the SMBus testcases
  • Examples showing how to connect and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation also contains User's Guide and Release notes

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
SMBus Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.

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Frequently asked questions about I2C / I3C IP cores

What is SMBus Synthesizable Transactor?

SMBus Synthesizable Transactor is a I2C / I3C IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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