Simulation VIP for LPDDR6

Speed

• 80 Mbps to 14400 Mbps

Device Density

• Supports a wide range of device densities from 4Gb to 64Gb. Dual channel sub-channel configuration. bank architecture: Four bank groups per sub-channel

General DDR Functionality

• Activation, precharge, and mode register write and read, CAS, read, write, power down, refresh, self-refresh, PDX-NT, NT-write, NT-read, read DQ calibration, write FIFO, read FIFO, MPC, and RFM command and related timing checks
• Bank and chip state machine per sub channel
• Clock frequency change, clock stop, jitters timing checks
• Initialization sequence
• Mode registers with frontdoor and backdoor access
• Different physical mode registers for 3 FSP
• All command-to-command timings, training timings, and core AC timings checks
• Dynamic voltage and frequency switch(DVFSL/DVFSQ/DVFSH/DVFSB)
• VRCG enable/disable
• Self-refresh and power down checks
• Setup/hold checks for CS/CA/DQ and training feedback corruption
• Single ended and differential mode of CK, WCK, and RDQS
• Data bus inversion​
• tmargin relaxation support for all timing params which are of type physical

Training Modes

• WCK-DQ training
• ZQ calibration
• Read DQ calibration and offset calibration
• WCK2CK leveling
• RDQS and enhanced RDQS toggle modes
• DCA and read DCA
• Loopback mode
• WCK2DQ interval oscillator training
• Duty Cycle Monitor (DCM)

Write Clock

• WCK to CK ratio: 2:1
• WCK sync off timing and sync extension
• WCK2DQ AC timings for low and high frequency
• WCK always on
• WCK static and toggle checks at full/half rate
• Write clock-related jitter timing parameter support
• WCK postamble checks

Burst Length

• 32 byte (BL24) and 64 byte (BL48)
• Interleaved 64 byte access when data rate is higher than 6400 Mbps (> 6400 Mbps)

Data Packet Format

• Data packet format with DBI/link ECC/on-die ECC/system meta mode enable/disable supported
• Burst sequence for read as per data packet format
• Non FIXL packet detection during write in different mode (Default , Link Protection , onDieECC , SystemMeta , Dbi)  and checkers

RDQS Preamble and Postamble

• RDQS patterns at Half/full rate toggles
• RDQS pre shift
• All combinations of reads merging placed Tccd+n apart

Efficiency Mode

• Static
• Dynamic
• Efficiency mode for mixed packages
• Timing constraints between same die sub-channels when efficiency mode enabled
• MRW control in SEFF/DEFF mode

Refresh

• Refresh checks and optimized refresh​​
• Refresh rates and options to control the application of new rates
• Temperature-based refresh changes and core timing derating
• PASR and PARC
• RFM Training constraints

ECC

• Link ECC and EDC mode
  • SBE, MBE detection
  • SBE correction
• On-die ECC (separate memory)

PRAC

• Activation counter initialization
• PRAC core timing parameters
• Alert backoff protocol
• Checkers and configurations to modify PRAC behavior
• Backdoor PRAC alert assertion
• Added soma feature for Activation count of rows of all banks or per bank to get decrement by BAT value When RFMab/RFMpb command is issued

System Meta Mode

• Separate MDR memory to store Meta info
• Meta command decoding
• Meta command timings
• Wck2ck sync extension with meta commands

Command Clock Sync

• CK sync turn ON and OFF
• CK sync timings constraints
• Command Input edge and sync status validation

CA Parity

• CA parity check
• Alert assertion and mode register status update on parity fail
• Parity error injection through callback
• NOP commands issued prior to establishing CK sync state (including the NOP command used to initiate CK sync) are not subject to CA parity checking

FMR and Alert

• Fault detection and alert assertion
• Supported fault detection: PRAC, ECC/EDC, and CA parity
• Backdoor fault injection and alert assertion
• Alert clean on MRR or via ABO protocol for PRAC fault

Inter-rank timing

• Rank-to-rank timing checks using InterConnectDesc SOMA feature

Frequency Set Points

• Allows LPDDR6 to be switched between three different operating frequencies by duplicating mode register parameters commonly changed with operating frequency

Exploration Mode

• VIP acts as a passive monitor without driving data and only checks for the command protocols: Read, MRR, and write

MPC

• Supports all 6 MPC commands

Latency and Frequency Table

• Checks all read and write latency requirements for a given frequency with related MR settings

ODT

• Support for dynamic write non-target ODT including PDX-NT command

Duty Cycle Adjuster

• Support for controlling the duty cycle of RDQS/DQ during Reads and WCK duty cycle adjustment

• Long and Short VREFCS return time
• Delay from VREFCS Update to RESET DRAM CS Counter/Reset Compare results
• Valid Clock/Write Clock Requirement after CS input
• WCK differential validation during training
• WCK frequency validation w.r.t WCKFM settings
• CST FSPOP and FSPWR settings validation at CST entry
• Setup/Hold check on DQ during vRef CS latch time

• Long and Short VREFCS return time
• Delay from VREFCA Update to RESET DRAM LFSR/Reset Compare results
• Valid Clock/Write Clock Requirement after CA PRBS pattern
• WCK differential validation during training
• WCK frequency validation w.r.t WCKFM settings
• CBT FSPOP and FSPWR settings validation at CBT entry
• Setup/Hold check on DQ during vRef CA latch time

• Support for WCK2DQ interval oscillator training along with the checkers and timers

• Command Truth Table support for x6 mode
• LPDDR6CK SYNC operation x6
• LPDDR6 Mode Register Read (MRR)x6 Mode
• LPDDR6 Data packet format for x6 devices

• All the mode registers are supported including new MRs related to PPR, Fault registers, Serial IDs and ECC

Functional Coverage

Provides a rich functional coverage of the below.

• Command-to-command timings coverage with all frequency range
• Inter-rank timing
• Mode register fields
• Efficiency and system meta mode
• Transaction fields

General Capabilities

• Soma reload
• Debug Ports
• Command and data callbacks
• Error control per sub-channel and Error injection through callback
• SystemC