Vendor: SmartDV Technologies Category: LPDDR

LPDDR5X Assertion IP

LPDDR5X Assertion IP provides an efficient and smart way to verify the LPDDR5X designs quickly without a testbench.

Overview

LPDDR5X Assertion IP provides an efficient and smart way to verify the LPDDR5X designs quickly without a testbench. The SmartDV's LPDDR5X Assertion IP is fully compliant with LPDDR5X draft JEDEC specification and JESD209-5B specification.

LPDDR5X Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR5X Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Supports 100% of LPDDR5X protocol draft JEDEC specification and JESD209-5B specification
    • Supports all the LPDDR5X commands as per the specs
    • Supports following device modes,
    • X8 Mode
    • X16 Mode
    • Supports WCK2CK Sync operation
    • Supports burst length 16 and 32
    • Supports for all mode registers programming
    • Supports Read DBI and Write DBI operation
    • Supports for Hybrid Refresh mode and Refresh credit mode
    • Supports for Write zero CAS command
    • Supports all data rates as per specification
    • Supports system ECC function.
    • Supports CA parity
    • Checks for following
    • Check-points include power on, Initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc,
    • All timing violations
    • Supports deep sleep mode
    • Supports power down mode and refresh operation
    • Supports ECC and CRC
    • Quickly validates the implementation of the LPDDR5X draft JEDEC specification and JESD209-5B specification
    • Bus-accurate timing for min, max and typical values
    • Constantly monitors LPDDR5X behavior
    • Protocol checker fully compliant with LPDDR5X draft JEDEC specification and JESD209-5B specification
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode
    • Supports Simulation mode (stimulus from SmartDV LPDDR5X VIP) and Formal mode (stimulus from Formal tool)
    • Rich set of parameters to configure LPDDR5X Assertion IP functionality

Block Diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
LPDDR5X AIP
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.

Learn more about LPDDR IP core

LPDDR flash: A memory optimized for automotive systems

Next-generation automotive systems are advancing beyond the limits of currently available technologies. The addition of advanced driver assistance systems (ADAS) and other advanced features requires greater processing power and increased connectivity throughout the vehicle.

SOCAMM: Modernizing Data Center Memory with LPDDR6/5X

Small Outline Compression-Attached Memory Module (SOCAMM) has made its way into the data center as an alternative to external CPU memory, due to its high performance, low power, memory capacity, and scalability.

Frequently asked questions about LPDDR IP

What is LPDDR5X Assertion IP?

LPDDR5X Assertion IP is a LPDDR IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this LPDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP