LPDDR DFI Assertion IP

DFI LPDDR Assertion IP provides an smart way to verify the ARM DFI LPDDR component of a SOC or a ASIC. The SmartDV's DFI LPDDR Assertion IP is fully compliant with standard DFI LPDDR Specification and provides the following features.

LPDDR DFI Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR DFI Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Specification Compliance
• Compliant with DFI version 2.0 or higher Specifications.
• Supports LPDDR devices compliant with JEDEC LPDDR SDRAM Standard JESD209A-1.pdf and JESD209B.pdf.
• Supports all Interface Groups.
• Supports Write Transactions with Data mask.
• Supports DRAM Clock disabling feature.
• Supports Data bit enable/disable feature.
• Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
• Supports frequency change protocol.
• Supports Low power control features.
• Supports Error signaling.
• Supports DFI Read/Write Chip Select.
• Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays.
• Constantly monitors DFI behavior during simulation.
• Protocol checker fully compliant with DFI 2.0 or higher Specifications.
• Assertion IP features
• Assertion IP includes:
• System Verilog assertions
• System Verilog assumptions
• System Verilog cover properties
• Synthesizable Verilog Auxiliary code
• Support Master mode, Slave mode, Monitor mode and Constraint mode.
• Supports Simulation mode (stimulus from SmartDV DFI LPDDR VIP) and Formal mode (stimulus from Formal tool).
• Rich set of parameters to configure DFI LPDDR Assertion IP functionality.

• Runs in every major formal and simulation environment.

• Detailed documentation of Assertion IP usage.
• Documentation also contains User's Guide and Release notes.