Vendor: ElectraIC Category: Post Quantum

PQC Co-Proc IP Core

co-processor supporting NIST’s selected Post-Quantum Cryptography (PQC) standards

CRYSTALS-Dilithium (ML-DSA) + 2 View all specifications

Overview

PQC Co-Proc IP core is a co-processor that supports NIST’s selected Post-Quantum Cryptography (PQC) standards, ML-KEM (Kyber), ML-DSA (Dilithium), SLH-DSA (SPHINCS+), and FN-DSA (Falcon). This IP is fully compliant with the NIST’s published standards, and offers countermeasures against Side-Channel Analysis attacks.

Key features

  • Supported Algorithms (algorithm set is customizable):
    • ML-KEM
      • FIPS-203 compliant
      • Key Generation, Encapsulation, Decapsulation
      • All security levels: ML-KEM-512, ML-KEM-768, ML-KEM-1024
    • ML-DSA
      • FIPS-204 compliant
      • Key Generation, Signature Generation, Signature Verification
      • All security levels: ML-DSA-44, ML-DSA-65, ML-DSA-87
    • SLH-DSA
      • FIPS-205 compliant
      • Key Generation, Signature Generation, Signature Verification
      • All security levels: SLH-DSA-SHAKE-128s/f, SLH-DSA-SHAKE-192s/f, SLH-DSA-SHAKE-256s/f
    • FN-DSA
      • Falcon Round 3 Submission compliant. Will be updated with FIPS-206 upon its publication
      • Signature Verification
      • All security levels: Falcon-512, Falcon-1024
  • Optional Side-Channel Analysis and Fault Injection attacks countermeasures (e.g., masking)
  • AXI4 interface for system integration available upon request
  • Crypto-agility: Modifications to existing implementations (e.g., new countermeasures) and new algorithms can be implemented by re-programming the RISC-V core’s firmware

Block Diagram

What’s Included?

  • Encrypted Netlist
  • Synthesis Scripts
  • Firmware (binary)
  • Comprehensive Documentation

Specifications

Identity

Part Number
EIP-30010002
Vendor
ElectraIC
Type
Silicon IP

Security

Crypto Algorithm
CRYSTALS-Dilithium (ML-DSA) , CRYSTALS-Kyber (ML-KEM) , FALCON

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Turkey

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Frequently asked questions about Post-Quantum Cryptography IP cores

What is PQC Co-Proc IP Core?

PQC Co-Proc IP Core is a Post Quantum IP core from ElectraIC listed on Semi IP Hub.

How should engineers evaluate this Post Quantum?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Post Quantum IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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