Vendor: T2M GmbH Category: Multi-Protocol PHY

PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC

To support high-bandwidth applications, PCIe 3.0 PHY IP provides a low-power, multi-lane, high-performance design.

TSMC 12nm FFC In Production View all specifications

Overview

To support high-bandwidth applications, PCIe 3.0 PHY IP provides a low-power, multi-lane, high-performance design. The PCIe 3.0 IP complies with the PIPE 4.3 standard and supports the whole spectrum of PCIe 3.0 Base applications. To enable PCIe 3.0 traffic at 8Gbps, the IP combines high-speed mixed signal circuits. Both the 2.5Gbps PCIe 1.0 data rate and the 5.0Gbps PCIe 2.0 data rate are backward compatible with it. The PCIe 3.0 IP may satisfy the needs for various channel circumstances since it supports both TX and RX equalisation approaches.

Key features

  • Compliant with PCIe 3.0 Base Specification
  • Compliant with PIPE 4.3
  • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
  • Supported physical lane width: x4
  • Supported parallel interface: 32-bit
  • Supported input reference clock: 100 MHSupported parallel interface data clock: 62.5 MHz, 125 MHz, and 250 MHz
  • Supporting low power operation with configurable setting in power state P1/P2/L1 PM Substates:PLL control, reference clock control, and embedded power gating control
  • Silicon Proven in TSMC 12FFC
  • Operating Voltage: 0.9V, 0.95V, 1.2V and 1.8V
  • Providing robust testability by low-cost Build-In Self-Test (BIST) via near-end analog and external loopback interface as well as far-end analog/digital loopback interface

Block Diagram

What’s Included?

  • GDSII & layer map
  • Place-Route views (.LEF)
  • Liberty library (.lib)
  • Verilog behaviour model
  • Netlist & SDF timing
  • Layout guidelines, application notes
  • LVS/DRC verification reports

Files

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 12nm FFC In Production

Specifications

Identity

Part Number
PCIe 3.0 Serdes PHY IP in 12FFC
Vendor
T2M GmbH

Provider

T2M GmbH
T2M GmbH is the leading Global Technology Company supplying state of the art complex semiconductor connectivity IPs and KGDs, enabling the creation of complex connected devices for Mobile, IoT and Wearable markets. T2M's unique SoC White Box IPs are the design database of mass production RF connectivity chips supporting standards including Wifi, BT, BLE, Zigbee, NFC, LTE, GSM, GNS. They are available in source code as well as KGD for SIP / modules. With offices in USA, Europe, China, Taiwan, South Korea, Japan, Singapore and India, T2M’s highly experienced team provides local support, accelerating product development and Time 2 Market.

Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC?

PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC is a Multi-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc In Production.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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