Vendor: SMIC Category: Multi-Protocol PHY

SMIC 55nm LL SSTL_18/ SSTL_2/ LPDDR/ LVTTL COMBO interface for DRAM application

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SMIC 55nm LL In Production View all specifications

Key features

  • SSTL_18/ SSTL_2/ LPDDR/ LVTTL COMBO interface for DRAM application;
  • 2).Suppport ONFI3.1/Toggle2.0 interface;
  • 3).SMIC 55nm Logic Low Leakage Salicide 1.2V/1.8V/2.5V Process;
  • 4).Cell Size (Width * height) 35um * 325um with DUP stagger bonding pads;
  • 5).Work voltage: 1.8V/2.5V/3.3V;
  • 6).Programmable driven-strength; programmable ODT, optional pullup,pulldown resistor; support data rate up to 667Mbps;
  • 7).Suitable for 7, 8, 9 and 10 layers application;

Silicon Options

Foundry Node Process Maturity
SMIC 55nm LL In Production

Specifications

Identity

Part Number
SP55NLLD2NP_MEMIO_COMBO
Vendor
SMIC

Provider

SMIC
HQ: China
Semiconductor Manufacturing International Corporation ("SMIC"; NYSE: SMI; SEHK: 981) is one of the leading semiconductor foundries in the world and the largest and most advanced foundry in mainland China. SMIC provides integrated circuit (IC) foundry and technology services at 0.35-micron to 28-nanometer. Headquartered in Shanghai, China, SMIC has a 300mm wafer fabrication facility (fab) and a 200mm mega-fab in Shanghai; a 300mm mega-fab in Beijing and a majority owned 300mm fab for advance nodes under development; a 200mm fab in Tianjin; and a 200mm fab project under development in Shenzhen. SMIC also has marketing and customer service offices in the U.S., Europe, Japan, and Taiwan, and a representative office in Hong Kong.
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Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is SMIC 55nm LL SSTL_18/ SSTL_2/ LPDDR/ LVTTL COMBO interface for DRAM application?

SMIC 55nm LL SSTL_18/ SSTL_2/ LPDDR/ LVTTL COMBO interface for DRAM application is a Multi-Protocol PHY IP core from SMIC listed on Semi IP Hub. It is listed with support for smic In Production.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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