Vendor: Chip Interfaces ApS Category: JESD204

JESD204 Verification IP

This JESD204 Verification IP provides an and efficient solution for verifying and debugging these standards in a UVM simulation e…

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Overview

This JESD204 Verification IP provides an advanced and efficient solution for verifying and debugging these standards in a UVM simulation environment.

The verification IP helps reduce time to test, accelerate verification process and ensures a high quality for the end-product. The JESD204 VIP is prepared for seamless functionality on all major simulators with UVM support and can be used only for JESD204 IPs from Chip Interfaces.

JESD204 Verification IP provides an advanced and efficient solution for verifying and debugging JESD204B, JESD204C, and JESD204D standards in a UVM simulation environment, based on a verification IP. The driver will send test case controlled JESD traffic on the Serdes interface to the DUT RX. DUT TX traffic will be received and monitored.

Running regression for coverage is supported and the solution is delivered with Integration Test environment to the Chip Interfaces JESD204 IP, such that is ready to test for a seamless out of the box experience.

Key features

  • Supports 32bit data width per converter
  • Supports multiple samples per converter per frame cycle
  • Supports up to 24 lanes
  • Supports 8b 10b link layer functions.
  • Supports 64b 66b link layer functions
  • Scrambling
  • Forward Error Correction (FEC) – For JESD204C
  • Reed-Solomon FEC (RS-FEC) – For JESD204D
  • RS-FEC encoding, 64b 66b, 64b 80b and 8b 10b
  • Extensive error injection and detection
  • Built-in protocol checks
  • Supports Lane alignment monitoring, correction and character replacement

Block Diagram

JESD204 Verification IP block diagram

Benefits

  • Test Environment: JESD204 IP is Tested against a VIP model in UVM regression for full functional coverage
  • Silicon Agnostic: Designed in Verilog and targeting both ASICs and FPGAs
  • Interoperability Tested: JESD204 IP is interoperability tested with
    • All leading PHY providers
    • Key data converter ADC & DAC providers
  • PHY Integration: PHY Integration support with additional hours or off the shelf PHY integration package for quick and efficient  deployment
  • Active Support: All support is actively provided by engineers directly

What’s Included?

  • The IP Core can be delivered in Source code or Encrypted format.
  • The following deliverables will be provided with the IP Core license:
    • Solid documentation, including User Manual and Release Note.
    • Simulation Environment, including Simple
    • Testbed, Test case, Test Script and Random Tests.
    • Error Scenario Tests and Basic and Directed Protocol tests (optional).
    • Access to support system and direct support from Comcores Engineers.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
JESD204 Verification IP
Vendor
Chip Interfaces ApS

Provider

Chip Interfaces ApS
HQ: Denmark
Chip Interfaces is your trusted partner for digital high-performance IP cores that meet the demanding requirements of next-generation applications. With a proven track record of delivering cutting-edge IP solutions, Chip Interfaces is a partner you can trust for your next project. We consider ourselves at the forefront of innovation, empowering chip designers to achieve exceptional performance and reliability, through significant investments in next generation technologies. Our wide range of digital IP cores encompasses JESD204, MIPI, Interlaken, CPRI/eCPRI, and RSFECs. Chip Interfaces silicon-agnostic and customizable IPs are interoperability tested with leading PHY providers, verified using the latest UVM regression techniques, and validated in test beds to ensure seamless integration with a wide range of other components and hardware platforms. This commitment to interoperability, verification and validation simplifies the design process and minimizes the risk of integration issues and ensures quality. We provide comprehensive support throughout the entire IP implementation process, and Chip Interfaces offers direct support from the engineers who designed and developed the IP cores. This unparalleled access to IP experts ensures timely and accurate guidance, enabling faster time to market. Our commitment to quality and excellence, coupled with our true wish to make our customers succeed, positions us as a trusted partner for your next project.
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Learn more about JESD204 IP core

JESD204 Frame Mapping explained from converter samples to lanes

The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Multiple ways JESD204 performs bitstream alignment

Bitstream alignment is a function of the Receiver (RX), as seen in the figure below it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes.

Frequently asked questions about JESD204 IP cores

What is JESD204 Verification IP?

JESD204 Verification IP is a JESD204 IP core from Chip Interfaces ApS listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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