Vendor: SmartDV Technologies Category: HBM

HBM2E DFI Assertion IP

DFI HBM2E Assertion IP provides an efficient and smart way to verify the DFI HBM2E designs quickly without a testbench.

Contact Provider Request Datasheet

Overview

DFI HBM2E Assertion IP provides an efficient and smart way to verify the DFI HBM2E designs quickly without a testbench. The SmartDV's DFI HBM2E Assertion IP is fully complian with standard DFI HBM2E Specification.

HBM2E DFI Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

HBM2E DFI Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Compliant with DFI version 4.0 or 5.0 Specifications.
    • Supports HBM2E devices compliant with JEDEC HBM2E DRAM Standard JESD235B and JESD235C.
    • Supports all Interface Groups.
    • Supports Write Transactions with Data mask
    • Supports DRAM Clock disabling feature.
    • Supports Data bit enable/disable feature.
    • Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
    • Supports frequency change protocol.
    • Supports Low power control features.
    • Supports Error signaling.
    • Supports DFI Read/Write Chip Select.
    • Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays
    • Constantly monitors DFI behavior during simulation.
    • Protocol checker fully compliant with DFI 4.0 or 5.0 Specifications.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV HBM2E VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure HBM2E Assertion IP functionality.

Block Diagram

HBM2E DFI AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
HBM2E DFI AIP
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about HBM IP core

Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference

LLM inference is increasingly memory-bound, and HBM cost per GB now dominates system cost. Today’s HBM stacks include short on-die ECC, which tightens binning, raises price, and locks reliability policy inside the device. This paper asks a simple question: can we tolerate a much higher raw HBM bit error rate (BER) and still keep end-to-end correctness and throughput, without changing the HBM PHY or the fixed 32B transaction size?

High Bandwidth Memory Evolution from First Generation HBM to the Latest HBM4

HBM4 is the latest generation of the High Bandwidth Memory (HBM) that has become analogous to the Artificial Intelligence (AI) boom that is everywhere in today’s world. HBM is also increasingly being used in other applications like Data centers, autonomous driving systems, servers, cloud computing just to mention few domains where bandwidth and performance in a key requirement.

Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure

High-Bandwidth Memory (HBM) delivers exceptional bandwidth and energy efficiency for AI workloads, but its high cost per bit, driven in part by stringent on-die reliability requirements, poses a growing barrier to scalable deployment. This work explores a systemlevel approach to cost reduction by eliminating on-die ECC and shifting all fault management to the memory controller.

High Bandwidth Memory (HBM) Model & Verification IP Implementation - Beginner's guide

With ever increasing need for very high operating frequency of graphics (GPU) or general purpose (CPU) processors, the limited memory bandwidth forms a bottleneck to extract maximum performance out of a system. To add to this, low power consumption, form factor of the memory devices also play significant roles in optimal and efficient solutions.

Frequently asked questions about LPDDR IP

What is HBM2E DFI Assertion IP?

HBM2E DFI Assertion IP is a HBM IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this HBM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HBM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP