Vendor: Truechip Solutions Category: HBM

HMC2 Verification IP

The HMC Verification IP provides an effective & efficient way to verify the HMC components of an ASIC/FPGA or SoC i.e.

Contact Provider Request Datasheet

Overview

The HMC Verification IP provides an effective & efficient way to verify the HMC components of an ASIC/FPGA or SoC i.e. Host or Device. The HMC VIP is fully compliant with Standard HMC Version 2.0 specifications from HMCC. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design time and the simulation time.

Key features

  • Compliant with Standard HMC Version 2.0 specification.
  • Supports 4GB configuration - 256 memory banks and 8GB configuration – 512 memory banks.
  • Supports Closed-bank memory architecture.
  • Supports Built-in memory controller for each vault – Automatic refresh control over all temperatures.
  • Supports internal ECC data correction.
  • Supports advanced RAS features including data scrubbing.
  • Supports Post-assembly repair capability.
  • Supports In-field repair for ultimate reliability.
  • supports 16 Lane(Full width) , 8 Lane(Half width), 4 Lane(Quarter width) full duplex serialized Link.
  • Supports PRBS15 as well as PRBS31 scrambler/descrambler Modes.
  • Supports Up to 320 GB/s effective bandwidth.
  • Packet based data/command interface.
  • Supports 16,32,48,64,80,96,112,128 and 256 byte references per request.
  • Supports Error detection for packets with automatic retry.
  • Power Management supported per link.
  • Reports various error signals, which can be used to check for any error.
  • Provides full control to the user to enable / disable various types of messages.
  • Supports full timing models or bus functional models.
  • Supports advanced SystemVerilog features like constrained random testing.
  • Supports dynamically configurable modes.
  • Strong Protocol Monitor with real time exhaustive programmable checks.
  • Supports Dynamic as well as Static Error Injection scenarios.
  • On the fly protocol checking using protocol check functions, static and dynamic assertion.
  • Built in Coverage analysis.
  • Provides a comprehensive user API (callbacks) in Monitor, Controller and Memory Model BFMs.
  • Graphical analyser to show transactions for easy debugging.

Block Diagram

HMC block diagram

Benefits

  • Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure highest levels of quality
  • Availability of Compliance & Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and cover points with connectivity example for all the components
  • Consistency of interface, installation, operation and documentation across all our VIPs
  • Provide complete solution and easy integration in IP and SoC environment

What’s Included?

  • HMC Controller BFM
  • HMC Device
  • HMC Monitor and Scoreboard
  • Test-Bench Configurations
  • Test Suite (Available in Source code)
    • Basic Protocol Tests
    • Directed & Random Tests
    • Error Injection Tests
    • Assertions & Cover Point Tests
  • Integration Guide, User Manual and Release Note

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
HMC
Vendor
Truechip Solutions

Provider

Truechip Solutions
HQ: USA
Truechip is a leading provider of Design and Verification solutions – which help you to accelerate your design, lowering the cost and the risks associated in the development of your ASIC, FPGA and SoC. Truechip is a privately held company, with a global footprint and with a strong and experienced leadership team. Truechip was established in 2008 with a Mission to:
  • To create world class Verification IP Solutions
  • To provide expert consultancy to ASIC & SoC Design companies
  • To design SOCs from Architecture to Working Silicon
Our Vision is to:
  • To be the leading provider of Semiconductor IP Solutions
  • To be a one-stop-shop for Design and Verification
Our Guiding Principles are:
  • Customer Success
  • Commitment to Quality
    • Quality of Products
    • Quality of Engineers
  • Best in class Customer Support
  • Ethics and Integrity
We at Truechip leverage the extensive domain knowledge and expertise from current associations to provide complete set of design and verification solutions to our customers.
Contact Truechip Solutions

Learn more about HBM IP core

Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference

LLM inference is increasingly memory-bound, and HBM cost per GB now dominates system cost. Today’s HBM stacks include short on-die ECC, which tightens binning, raises price, and locks reliability policy inside the device. This paper asks a simple question: can we tolerate a much higher raw HBM bit error rate (BER) and still keep end-to-end correctness and throughput, without changing the HBM PHY or the fixed 32B transaction size?

High Bandwidth Memory Evolution from First Generation HBM to the Latest HBM4

HBM4 is the latest generation of the High Bandwidth Memory (HBM) that has become analogous to the Artificial Intelligence (AI) boom that is everywhere in today’s world. HBM is also increasingly being used in other applications like Data centers, autonomous driving systems, servers, cloud computing just to mention few domains where bandwidth and performance in a key requirement.

Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure

High-Bandwidth Memory (HBM) delivers exceptional bandwidth and energy efficiency for AI workloads, but its high cost per bit, driven in part by stringent on-die reliability requirements, poses a growing barrier to scalable deployment. This work explores a systemlevel approach to cost reduction by eliminating on-die ECC and shifting all fault management to the memory controller.

High Bandwidth Memory (HBM) Model & Verification IP Implementation - Beginner's guide

With ever increasing need for very high operating frequency of graphics (GPU) or general purpose (CPU) processors, the limited memory bandwidth forms a bottleneck to extract maximum performance out of a system. To add to this, low power consumption, form factor of the memory devices also play significant roles in optimal and efficient solutions.

Frequently asked questions about LPDDR IP

What is HMC2 Verification IP?

HMC2 Verification IP is a HBM IP core from Truechip Solutions listed on Semi IP Hub.

How should engineers evaluate this HBM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HBM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP