Vendor: CAST Category: Video Processing

Hardware RTP Stack for H.264 Stream Decapsulation

Implements a Real Time Transport Protocol (RTP) hardware stack that extracts H.264/NAL streams encapsulated in RTP packets.

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Overview

Implements a Real Time Transport Protocol (RTP) hardware stack that extracts H.264/NAL streams encapsulated in RTP packets.

The RTP2H264 core is compatible with RTP packets produced by CAST’s H.264 to RTP encapsulation core (H2642RTP). The output of the RTP2H264 can be directly connected to the input of an H.264 decoder core. Along with CAST’s UDP/IP hardware stack, the RTP2?264 core is ideal for offloading the demanding task of RTP/UDP/IP de-capsulation from a host processor, and enables H.264 video streaming even in processor-less SoC designs.

The core is easy to integrate in systems with or without a host processor. H.264 stream and RTP packet data can are input/output via dedicated streaming-capable interfaces, enabling direct connection to hardware video encoders and hardware stacks for UDP or TCP. Status and control registers are accessible by an AXI4-Lite interface.

The RTP2H264 core is available in RTL source or as a targeted FPGA netlist. Platforms integrating the core along H.264 decoder, UDP/IP, and eMAC cores, are also available from CAST, and can enable rapid development of video over IP systems.

Key features

  • RTP Decapsulation for H.264 NAL Streams
    • Compatible with RTP streams produced by CAST’s H264 to RTP encapsulation core.
    • Support for other RTP encapsulation stacks possible on request.
  • Easier Integration For Faster Development
    • Processor-less, standalone operation
    • AMBA® - AXI Interfaces
      • AXI4-Lite Control/Status register interfaces
      • AXI4-Streaming interfaces for packet data
    • Available pre-integrated with:
      • H.264 Video Decoder cores from CAST
      • UDP/IP Hardware Stack from CAST
      • CAST, Intel, Xilinx, or other third-party eMAC core

Block Diagram

RTP2H264 block diagram

Applications

  • The RTP2?264 core is suitable for a wide variety systems and devices featuring H.264 video streaming over IP networks. A sample block diagram of such systems is provided below.

What’s Included?

  • Synthesizable Verilog RTL or FPGA netlist
  • Testbench & sample test cases
  • Simulation & synthesis scripts
  • Documentation

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
RTP2H264
Vendor
CAST

Provider

CAST
HQ: USA
CAST is a silicon intellectual property (IP) developer, aggregator, and integrator providing IP cores and subsystems since 1993. Our product line features both leading-edge and standards-based digital IP, including compression engines and image processing functions; 8051 microcontrollers and low-power 32-bit BA2X™ processors; industry-leading automotive interfaces; a complete family of SoC security modules; and a variety of peripherals, interfaces, and other IP cores. Our goal is to maximize IP benefits for our customers by delivering high quality, easy to use, cost effective solutions for real system development challenges. We minimize customer risk through rigorous development standards, complete deliverables with comprehensive documentation, and superlative customer support. We maximize customer value thorough competitive pricing and simple licensing—including royalty-free options—and long-term partnerships with all leading silicon providers and select technology leaders. Our product standards and business practices have been uniquely honed through successful projects with hundreds of systems designers since the very beginnings of the IP industry, making CAST one of the best IP partners available.
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Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is Hardware RTP Stack for H.264 Stream Decapsulation?

Hardware RTP Stack for H.264 Stream Decapsulation is a Video Processing IP core from CAST listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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