Vendor: WebM - Open Web Media Project Category: Video Processing

WebM VP8 Video Decoder Hardware IP

The WebM VP8 (G1) hardware decoder brings an unprecedented level of performance to enable all kinds of WebM video applications.

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SMIC 40nm Silicon Proven View all specifications

Overview

The WebM VP8 (G1) hardware decoder brings an unprecedented level of performance to enable all kinds of WebM video applications. It is the first hardware decoder in the market to encompass full WebM video support, significantly extending the video playback time of Internet-connected and HTML5-enabled battery operated devices.

Intended for chipsets targeting multimedia devices (Smart DTVs, HD set-top boxes, smart phones, tablets, Chromebooks, etc.), the WebM VP8 G1 Decoder is built on silicon-proven designs deployed in millions of chips worldwide, and provides semiconductor manufacturers with a minimal risk solution for integrating high performance video capability to their chipsets.

The video decoder design is exceptionally fast, requiring less than 100MHz clock frequency to decode 1080p video at 30 fps, and can even achieve 60fps decode for 2160p VP8 video through multi-core implementation. The core supports unlimited VP8 multi-channel decoding, enabling simultaneous playback of up to ten SD streams. It uses unique pre-fetching and buffering mechanisms to enable smooth operation with low-end SDRAMs, realizing significant savings in power and overall chip design and manufacturing costs.

the G-Series 1 is highly power efficient, consuming less than 50 milliwatts for HD video decoding, and less than 10 milliwatts for SD video.

Key features

  • Silicon area: 383kGates, 40kBytes of single port SRAM
  • Synthesizable clock frequency: up to 290 MHz (TSMC65nm LP, topographical synthesis)
  • Easy back-end: Single clock domain;low number of isolated single port SRAM and clock gating elements; no dual port memories.
  • Performance configuration: choose internal memory size according to your resolution requirement - up to 2160p.
  • Target SoC configuration: choose the bus protocol interface from AHB, AXI, OCP and APB.
  • Easy application development: simple application programming interface (API)

Block Diagram

G1 VP8 Video Decoder block diagram

Applications

  • Smart phones, tablets, smart DTVs, set-top boxes, Chromebooks, etc.

What’s Included?

  • RTL source code (VHDL or Verilog) with RTL test bench and test data.
  • ANSI C source code for hardware drivers, with software test bench and test data.
  • Technical documentation: hardware and software integration guides and application programming interface (API) manuals.
  • Reference C-model (bit-accurate with RTL)

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
SMIC 40nm 40nm 400 nm Silicon Proven

Specifications

Identity

Part Number
G1 VP8 Video Decoder
Vendor
WebM - Open Web Media Project

Provider

WebM - Open Web Media Project
HQ: Finland
Intended for chipsets and ASICs targeting multimedia devices (HD set-top boxes, mobile devices, netbooks, webcams, etc.), the WebM encoder and decoder hardware IP is built on technology developed by Google’s Oulu, Finland office. This group has developed silicon-proven designs deployed in hundreds of millions of chips worldwide, and provides semiconductor manufacturers with a minimal-risk solution for integrating WebM video capability with their chipsets. The WebM video hardware IP designs support encoding and decoding WebM/VP8 video up to 1080p resolution. Implemented as RTL source code (VHDL or Verilog), both WebM IP designs are currently available to semiconductor companies having firm plans to ship VP8-supporting products. A written, no-cost agreement is required. Visit www.webmproject.org/hardware for more details.
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Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is WebM VP8 Video Decoder Hardware IP?

WebM VP8 Video Decoder Hardware IP is a Video Processing IP core from WebM - Open Web Media Project listed on Semi IP Hub. It is listed with support for smic Silicon Proven.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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