Provider
Cadence Design Systems, Inc.
HQ:
USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem.
Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster.
The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements.
Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Learn more about GDDR IP core
This paper will include a short review of the key features of DDR, GDDR and MobileDDR memory architectures, covering power, speed and cost characteristics as well as key functionality differences that can impact overall system architecture. Using real system design experiences each of the main memory architectures will be used to address system design challenges of sustained bandwidth, reliability, access priority, power savings, and interface requirements.
Large Language Models (LLMs) have gained popularity in recent years, driving up the demand for inference. LLM inference is composed of two phases with distinct characteristics: a compute-bound prefill phase followed by a memory-bound decode phase. This paper proposes SPAD (Specialized Prefill and Decode hardware), adopting a less-is-more methodology to design specialized chips tailored to the distinct characteristics of prefill and decode phases.
HBM4 is the latest generation of the High Bandwidth Memory (HBM) that has become analogous to the Artificial Intelligence (AI) boom that is everywhere in today’s world. HBM is also increasingly being used in other applications like Data centers, autonomous driving systems, servers, cloud computing just to mention few domains where bandwidth and performance in a key requirement.
The rapid evolution of artificial intelligence (AI) is reshaping the technological landscape, driving unprecedented demands on computing infrastructure. At the heart of this transformation lie innovations in intellectual property (IP) that enable scalable, efficient, and performance-driven AI factories.
This white paper will discuss the design challenges that IC designers are facing when developing the new GDDR 7 high-performance memory interface and highlight some of the possible solutions to overcome these challenges, ensuring compliance and robustness of the GDDR7 memory interface.
The rapid evolution of artificial intelligence (AI) over the past decade has reshaped the way we interact with technology and transformed industries across the board. From early predictive models and voice assistants to today’s highly complex generative AI systems, we are witnessing the dawn of a new era: AI 2.0.
