Standard Cell PowerSlash(TM) Library IP, 8 tracks, UMC 0.11um eFlash/HS process
UMC 0.11um eFlash/HS process 8-Track Generic Core Cell Library.
- UMC
- 110nm
Standard cell libraries are fundamental building blocks for ASIC and SoC design, providing a set of pre-characterized logic cells used in digital circuit implementation.
These libraries include essential components such as logic gates, flip-flops, latches, and buffers, enabling efficient synthesis and physical design flows.
This catalog allows you to compare standard cell libraries from leading vendors based on performance, power consumption, area, and process node compatibility.
Whether you are targeting high-performance computing, low-power mobile designs, or cost-sensitive applications, you can find the right standard cell library for your project.
Standard Cell PowerSlash(TM) Library IP, 8 tracks, UMC 0.11um eFlash/HS process
UMC 0.11um eFlash/HS process 8-Track Generic Core Cell Library.
Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 12-Track Generic Core Cell Library.
Standard Cell (Ultra High Speed) Library IP, LVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 12-Track Generic Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 12-Track Generic Core Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 12-Track Generic Core Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm SP process
UMC 55nm SP/HVT Low-K Logic process UHS Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm eHV process
UMC 55nm HV/HVT Low-K Logic process high speed Standard Core Library.
Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 55nm SP process
UMC 55nm SP/RVT Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 55nm SP process
UMC 55nm SP/HVT Logic process 7-Track Mini Cell Library.
Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 7-Track Mini-Library.
Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Low-K Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Low-K Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track Cell Library with LPLUS (C38 RVT).
Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track Cell Library with LMINUS (C30 RVT).
Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library wtih LPLUS (C38).
Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library.