UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track eco_m1 cell library (C35)
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track eco_m1 cell library (C35)
- UMC
- 28nm
- HPC
- Pre-Silicon
Standard cell libraries are fundamental building blocks for ASIC and SoC design, providing a set of pre-characterized logic cells used in digital circuit implementation.
These libraries include essential components such as logic gates, flip-flops, latches, and buffers, enabling efficient synthesis and physical design flows.
This catalog allows you to compare standard cell libraries from leading vendors based on performance, power consumption, area, and process node compatibility.
Whether you are targeting high-performance computing, low-power mobile designs, or cost-sensitive applications, you can find the right standard cell library for your project.
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track eco_m1 cell library (C35)
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track eco_m1 cell library (C35)
Standard Cell (Generic) Library IP, UMC 0.13um process
UMC 0.13um Logic process, DFY Cell Library.
Standard Cell (RTC) Library IP, UMC 55nm ULP process
UMC 55nm ULP/uHVT LowK Logic Process 2.5 V OD 3.3 V device RTC Core Library
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process Powerlash Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library (C35).
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LPLUS (C38).
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LMINUS (C30 RVT).
Standard Cell PowerSlash(TM) Library IP, LVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic process 9-Track POWERSLASH standard Core Cell Library (C35).
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library (C35).
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Generic Core Cell Library wtih LPLUS (C38).
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LMINUS (C30).
Standard Cell PowerSlash(TM) Library IP, HVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic process 9-Track POWERSLASH Core Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/HVT Logic and Mixed-Mode process 7-Track POWERSLASH Kit Cell Library C35.
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library with LPLUS (C38).
Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process 12-Track high performance Cell Library.
Standard Cell (Ultra High Speed) Library IP, LVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Low-K Logic process 12-Track high performance Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Low-K Logic process 12-Track Standard Cell Library.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process high density Core Cell Library.
Standard Cell (Generic) Library IP, 10-track, RVT, UMC 90nm SP process
UMC 90nm SP Logic Low-K process standard Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.25um process
UMC 0.25um Logic process standard Cell Library.