Input 5M-200MHz, output 12.5M-200MHz, frequency synthesizable PLL with power/ground pad, UMC 0.13um LL Logic/FSG process.
- UMC
- 130nm
- LL
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Input 5M-200MHz, output 12.5M-200MHz, frequency synthesizable PLL with power/ground pad, UMC 0.13um LL Logic/FSG process.
PLL IP, Input: 10MHz - 200MHz, Output: 25MHz - 400MHz, UMC 0.13um SP/FSG process
Output frequency 25M~400MHz PLL, UMC 0.13um SP/FSG Logic process.
Input 133MHz - 266MHz, output clock_1X 133MHz - 266MHz, output clock_2X 266MHz - 533MHz, output clock_4X 533MHz-1066MHz, frequenc…
PLL (Frequency Synthesizer) IP, Input: 66.66MHz, Output: 400MHz - 800MHz, UMC 0.13um HS/FSG process
Input 66.66MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 0.13um HS/FSG Logic process.
Input 20M-200MHz, output 250M-500MHz (with duty ratio 40%~60%) and 125M~ 250MHz (with duty ratio 45%~ 55%), frequency synthesizab…
PLL IP, Input: 372M - 540MHz, Output: 5MHz - 400MHz, UMC 0.13um HS/FSG process
Input 372M ~ 540MHz, output 5M ~ 400MHz, PLL, UMC 0.13um HS/FSG Logic process.
Input 5M-200MHz, output 12.5M-300MHz, frequency synthesizable PLL with power/ground pad, UMC 0.11um CMOS Image Sensor process.
Input 5M-200MHz, output 12.5M-300MHz, frequency synthesizable PLL, UMC 0.11um CMOS Image Sensor process.
PLL IP, Input: 32.768KHz, Output: 12MHz - 48MHz, UMC 0.11um HS/FSG process
Input 32.768KHz, output 12M-48MHz, PLL, UMC 0.11um HS/Copper Logic process.
RC Oscillator IP, Output: 50MHz, UMC 90nm SP process
Internal-RC, trimmable fixed frequency 50MHz.
Ring Oscillator IP, Output: 12KHz, UMC 90nm Logic process
12KHz Ring OSC.
RC Oscillator IP, Output: 12KHz, UMC 65nm SP process
Internal-RC, trimmable fixed frequency 12KHz.
RC Oscillator IP, Output: 50MHz, UMC 0.18um G2 process
Internal-RC, frequency 50MHz.
RC Oscillator IP, Output: 25MHz / 33MHz, UMC 0.18um eFlash/G2 process
UMC 0.18um eFlash process, Internal-RC, trimmable frequency selected 25MHz/33MHz, VCCA=1.2V~1.8V, VBG=0.615.
RC Oscillator IP, Output: 20MHz, UMC 0.18um G2 process
Internal-RC, trimmable frequency 20MHz, VCCA=1.6V~2.0V VBG=0.615V, UMC 0.18um GII Logic process.
RC Oscillator IP, Output: 50MHz / 70MHz, UMC 0.18um G2 process
Internal-RC, trimmable frequency selected 50MHz/70MHz.
RC Oscillator IP, Output: 70MHz, UMC 0.11um HS/FSG process
Internal-RC, trimmable fixed frequency 70MHz.
DDR DLL IP, Input: 200MHz - 333MHz, Output: 200MHz - 333MHz, UMC 90nm SP process
Input 200-333MHz, output 200-333MHz, DDR2 DLL, UMC 90nm SP/RVT Low-K Logic process.
DDR DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 65nm SP process
Input 100-400MHz, output 100-400MHz, DDR2 DLL, UMC 65nm SP/RVT Low-K Logic process.
DDR DLL IP, Input: 80MHz - 320MHz, Output: 6.25%-50% Delay, UMC 55nm SP process
Input 80-320MHz, output 6.25%~50% delay, 80-320MHz, DDR2 DLL, UMC 55nm SP/RVT Low-K Logic process.