SMIC18 General process, Multi-Voltage IO, High ESD perfermance
SMIC18 General process, Multi-Voltage IO, High ESD perfermance
SMIC18 General process, Multi-Voltage IO, driver current: 10mA~80mA
SMIC18 General process, Multi-Voltage IO, driver current: 10mA~80mA
SMIC13 High Speed process, 1.2/1.5V High Speed Transceiver Logic IO
VeriSilicon SMIC 0.13um 1.2V/1.5V HSTL I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing Int…
VeriSilicon SMIC 0.18um 1.8V/3.3V SSTL3 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing In…
VeriSilicon SMIC 0.15um 1.5V/3.3V SSTL3 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing In…
VeriSilicon SMIC 0.18um 1.8V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing In…
VeriSilicon SMIC 0.15um 1.5V/3.3V SSTL2 I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing In…
SMIC 0.18um LVDS Transceiver/Receiver
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS.
The PCI-X transceiver is a IP version of PCI-X I/O pads, which is fully compatible with PCI-X R1.0 specification.
Analog PLL suitable for high speed clock generation.
Analog PLL suitable for high speed clock generation.
Analog PLL suitable for high speed clock generation.
Power-On-Reset circuit uses the RC delay to generate the system reset pulses.
Power-On-Reset circuit uses the RC delay to generate the system reset pulses.
SMIC 0.18um 3.3v Power Regulator
Power Regulator, also called Voltage Regulator, is an on-chip device which provides suitable power supply for the core from an ex…
A programmable analog PLL suitable for high speed clock generation.
Power-On-Reset circuit uses the RC delay to generate the system reset pulses
Power-On-Reset circuit uses the RC delay to generate the system reset pulses.
DDR4 IO for memory PHY, 3200Mbps on SMIC 40nm
The DDR4 IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device.
Low power XTAL oscillator, 4M~40MHz on SMIC 40nm
The present IP is a crystal oscillator.