Thread Synthesis and Reordering attachment IP for use with random access masters to HBM IP
- SRAM
Embedded memory IP cores are fundamental components in modern SoC and ASIC designs, providing fast and efficient on-chip data storage for processors, accelerators, and peripherals.
These IP cores encompass a broad range of volatile and non-volatile memory technologies, including SRAM for high-speed data storage, ROM for fixed program and boot code storage, register files for processor and accelerator architectures, as well as EEPROM, eFuse/OTP, and MTP (Multiple-Time Programmable) memories for configuration data, security credentials, device calibration, and permanent system information.
This catalog allows you to compare embedded memory IP cores from leading vendors based on density, access time, power consumption, and process node compatibility.
Whether you are designing high-performance processors, AI accelerators, automotive systems, or IoT devices, you can find the right embedded memory IP for your design.
Thread Synthesis and Reordering attachment IP for use with random access masters to HBM IP
Samsung 28nm Low Voltage Single-Port SRAM Compiler
VeriSilicon Samsung 28FDSOI Low Voltage Synchronous Single-Port SRAM compiler optimized for Samsung FDSOI 28nm process can flexib…
Samsung 28nm Low Power Single-Port SRAM Compiler
VeriSilicon Samsung 28FDSOI Low Power Synchronous Single-Port SRAM compiler optimized for Samsung FDSOI 28nm process can flexibly…
Dual Port SRAM compiler - TSMC 40 nm uLP - Memory optimized for high density and low power - Dual Rail - compiler range up to 288…
Single Port SRAM compiler - TSMC 180 nm BCD Gen2 - Memory optimized for high density and Low power - compiler range up to 320 k
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
Foundry sponsored - Single Port SRAM compiler - TSMC 90 nm LPeF - Memory optimized for high density and Low power - compiler rang…
Foundry sponsored - Single Port Register File compiler - TSMC 90 nm LPeF - Memory optimized for high density and high speed - com…
Single Port Register File compiler - TSMC 90 nm LPeF - Memory optimized for high density and high speed - Dual voltage - compiler…
This Physical Layer core gives you the ability to simultaneously read and write on every rising and falling edge.
This Physical Layer core gives you the ability to simultaneously read and write on every rising and falling edge.
UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral
UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral
UMC 28nm HPC Process PG Via ROM Compiler
UMC 28nm HPC Process PG Via ROM Compiler
UMC 40nm uLP process ULL Via1 ROM compiler
UMC 40nm uLP process ULL Via1 ROM compiler
UMC 40nm ultra low power via1 ROM complier
UMC 40nm ultra low power via1 ROM complier
UMC 55nm ULP/LowK Process via ROM compiler for well bias
UMC 55nm ULP/LowK Process via ROM compiler for well bias
UMC 55nm ULP/LowK Process via1 ROM compiler well bias
UMC 55nm ULP/LowK Process via1 ROM compiler well bias
UMC 55nm ULP Low-K process HVT via1 ROM
UMC 55nm ULP Low-K process HVT via1 ROM
UMC 55nm EFLASH Process Via ROM Memory complier
UMC 55nm EFLASH Process Via ROM Memory complier
UMC 28HPC process standard synchronous high density TCAM memory compiler
UMC 28HPC process standard synchronous high density TCAM memory compiler