Single Port SRAM Compiler IP, UMC 55nm SP process
UMC 55nm SP Low_K Logic process synchronous high density Single Port SRAM memory compiler.
- UMC
- 55nm
- SP
Embedded memory IP cores are fundamental components in modern SoC and ASIC designs, providing fast and efficient on-chip data storage for processors, accelerators, and peripherals.
These IP cores encompass a broad range of volatile and non-volatile memory technologies, including SRAM for high-speed data storage, ROM for fixed program and boot code storage, register files for processor and accelerator architectures, as well as EEPROM, eFuse/OTP, and MTP (Multiple-Time Programmable) memories for configuration data, security credentials, device calibration, and permanent system information.
This catalog allows you to compare embedded memory IP cores from leading vendors based on density, access time, power consumption, and process node compatibility.
Whether you are designing high-performance processors, AI accelerators, automotive systems, or IoT devices, you can find the right embedded memory IP for your design.
Single Port SRAM Compiler IP, UMC 55nm SP process
UMC 55nm SP Low_K Logic process synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process synchronous ultra high speed Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 55nm SP process
UMC 55nm SP/RVT+HVT Low-K Logic process synchronous high density Single Port SRAM memory compiler.
One Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process synchronous Low Power (PG-DC) using 0.425-Bit cell Single Port Register File memory compiler.
Single Port SRAM Compiler IP, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process synchronous Low Power (PG-DC) using 0.425-Bit cell Single Port SRAM memory compiler.
One Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process Low Power synchronous high density One Port Register File compiler.
Single Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process
UMC 55nm SP Low-K Logic process Low Power synchronous high density Single Port SRAM memory compiler with redundancy.
Single Port SRAM Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process Low Power synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.25um Logic process
UMC 0.25um Logic process synchronous high speed Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um MS process
UMC 0.18um Mixed-Mode process synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um CIS process
UMC 0.18um CMOS Image Sensor process synchronous high density Single Port SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.13um CIS process
UMC 0.13um 2P4M 1.5V CMOS Image Sensor process synchronous Single Port Register File SRAM compiler.
One Port Register File Compiler IP, UMC 0.11um SP/AE process
UMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous high density Single Port Register File SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.11um SP/AE process
UMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous High-density Single Port SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.11um LL/AE process
UMC 0.11um LL/AE (AL Enhancement) Logic process standard asynchronous high density Single Port Register File SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.11um LL/AE process
UMC 0.11um LL/AE (AL Enhancement) Logic process synchronous high density Single Port SRAM memory compiler.
ROM Compiler IP, UMC 65nm LL process
UMC 65nm LL Logic RVT Low-K process synchronous Via-1 ROM memory compiler.
ROM Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process synchronous Via-1 ROM memory compiler.
ROM Compiler IP, UMC 0.25um Logic process
UMC 0.25um process synchronous VIA1 programmable ROM compiler.
ROM Compiler IP, UMC 0.13um CIS process
UMC 0.13um CMOS Image Sensor process synchronous Via 1 ROM memory compiler.