Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
Silicon Storage Technology, Inc.
Category:
SRAM
memBrain™ Tile
Key features
- Multiplication happens through cell operation characteristics
- Summation happens along the word or bit line depending on configuration
- Multiple "Tiles" can be connected to support a large neural system
- Example tile full frame cycle time 10-30 us
- Depends on D-A and A-D power
- Energy is 0.3pJ per MAC with D/A+A/D @ 30 us frame cycle time
- Area with D to A input and A to D output blocks = 0.48 mm^2 on 40 nm (512×512 tile available, other Tiles in development)
Block Diagram
memBrain™ Tile block diagram
Specifications
Identity
Part Number
memBrain™ Tile
Vendor
Silicon Storage Technology, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about SRAM IP cores
What is memBrain™ Tile?
memBrain™ Tile is a SRAM IP core from Silicon Storage Technology, Inc. listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.