Vendor: SmartDV Technologies Category: HBM

HBM2E Synthesizable Transactor

HBM2E Synthesizable Transactor provides a smart way to verify the HBM2E component of a SOC or a ASIC in Emulator or FPGA platform.

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Overview

HBM2E Synthesizable Transactor provides a smart way to verify the HBM2E component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's HBM2E Synthesizable Transactor is fully compliant with standard HBM2E Specification and provides the following features.

Key features

  • Supports 100% of HBM2E protocol standard JESD235B,JESD235C and JESD235D.
  • Supports all the HBM2E commands as per the specs
  • Supports all types of timing and protocol violation detection
  • Supports burst length of 2 and 4
  • Supports Programmable READ/WRITE Latency timings
  • Supports Bank grouping
  • Supports 8, 16, 32, 48 and 64 banks per channel
  • Supports up to 8 channels per stack
  • Supports Extended Addressing
  • Supports Extended Write latency and Read latency
  • Checks for following
    • Check-points include power on, Initialization and power off rules
    • State based rules, Active Command rules
    • Read/Write Commands rules etc
    • All timing violations
  • Supports callbacks for user to get command data on bus
  • Supports All Mode registers programming
  • Supports DBIac write and read
  • Supports Legacy Mode and Pseudo Channel Mode Operation (64 DQ width for Pseudo Channel Mode)
  • Supports Self-Refresh Modes
  • Supports channel density of 1 GB to 128 GB
  • Supports 128 DQ width + Optional ECC pin support/channel
  • Supports ECC
  • Supports write data mask and data strobe features
  • Supports for power down features
  • Supports for input clock stop and frequency change
  • Supports for target row refresh mode
  • Supports for temperature compensated refresh reporting
  • Supports for IEEE standard 1500
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations

Block Diagram

HBM2E Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the HBM2E testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
HBM2E Transactor
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
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Frequently asked questions about LPDDR IP

What is HBM2E Synthesizable Transactor?

HBM2E Synthesizable Transactor is a HBM IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this HBM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HBM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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