The 4-bit programmable ECL low-frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3 which is able to scale the structure into maximum dividing ratio increasing. If the dividing ratio is set to 1, the input signal is switched to the output and the circuit is disabled. The differential circuit has high noise immunity.
The block is fabricated AMS BiCMOS 0.35 um technology
4-bit programmable ECL LF divider (1…15 dividing ratio )
Overview
Key Features
- AMS BiCMOS 0.35 um
- Differential structure
- Dividing ratio is regulated in the range of 1 …15 with step 1
- Input differential signal frequency up to 150 MHz
- Scalable structure
- Portable to other technologies (upon request)
Applications
- PLL frequency synthesizer
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
AMS BiCMOS 0.35 um
Maturity
silicon proven
Availability
Now
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