IP Catalog > Interface IP > Interconnect IP > Serdes IP > 12.5G Multiprotocol Serdes IP, Silicon Proven in UMC 28HPC

12.5G Multiprotocol Serdes IP, Silicon Proven in UMC 28HPC

Overview

The multi-protocol SerDes PHY consists of Serial ATA (SATA) conforming with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support for PIPE interface spec, Universal Serial Bus (USB) compliant with USB 3.0, USB 2.0 (USB Highspeed and Full speed), and USB 3.0 compliant with USB 3.0. Due to the provision of extra PLL control, reference clock control, and integrated power gating control, lower power consumption is obtained.
Additionally, because the aforementioned low power mode option is customizable, the PHY is extensively useful for a variety of situations with diverse power consumption considerations.

Key Features

  • A universal SERDES IP that operation from 1Gbps to 12.5 Gbps
  • Compatible with PCIe/USB3/SATA base Specification
  • Support 40-bit/32-bit/20-bit/16-bit parallel interface
  • Support for PCIe2(5.0Gbps), USB3.0(5.0Gbps) and SATA3(6.0Gbps)
  • Backward compatible with 2.5Gbps for PCIe
  • Backward compatible with 1.5Gbps, 3.0Gbps for SATA
  • Support flexible reference clock frequency
  • Support 100MHz differential reference clock input or output (with SSC optionally) in PCIe Mode
  • Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm
  • Support programmable transmit amplitude and Deemphasis
  • Support TX detect RX function in PCIe and USB3.0 Mode
  • Support Beacon signal generation and detection in PCIe Mode
  • Support LFPS signal generation and detection in USB Mode
  • Support Low Frequency Periodic Signalling (LFPS) generation and detection in USB3.0 Mode
  • Production test support is optimized through high coverage at-speed BIST and loopback
  • Integrated on-die termination resistors and IO Pads/Bumps
  • Embedded Primary & Secondary ESD Protection
  • ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA
  • Silicon Proven in UMC 28nm HPC

Applications

  • PC
  • Television
  • Data storage
  • Multimedia Devices
  • Recorders
  • Mobile devices

Deliverables

  • Application Note / User Manual
  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and Standard
  • Delay Format (SDF)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation

Technical Specifications

Maturity
In Production
Availability
Immediate
Request Info

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