The FastMath Pack is a math processing accelerator for the ARC HS family
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
- Arithmetic Units
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
The FastMath Pack is a math processing accelerator for the ARC HS family
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
ARC HS38x4 quad-core 32-bit processor with MMU, ARCv2 ISA, for embedded Linux applications
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
ARC HS38x2 dual-core 32-bit processor with MMU, ARCv2 ISA, for embedded Linux applications
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
ARC HS38 32-bit processor with MMU, ARCv2 ISA, for embedded Linux applications
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
ARC HS36x4 quad-core version of HS36 with I and D cache for high-performance embedded applications
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
ARC HS36x2 dual-core version of HS36 with I and D cache for high-performance embedded applications
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
ARC HS36 32-bit processor core, ARC V2 ISA, for embedded applications
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
ARC HS34x4 quad-core version of HS34 for real-time embedded applications
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
ARC HS34x2 dual-core version of HS34 for embedded real-time applications
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
ARC HS34 32-bit processor core, ARC V2 ISA, for embedded applications
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
The ARC-V™ RPX-100 series processors feature a dual-issue, 64-bit superscalar architecture for use in high performance applicatio…
ARC-V RHX Series Functional Safety Processor IP
The ARC-V™ RHX-110-FS, RHX-115-FS, RHX-110V-FS, and RHX-115V-FS functional safety processors simplify development of high-perform…
The ARC-V™ RHX-100 series processors feature a dual-issue, 32-bit superscalar architecture for use in applications where real-tim…
ARC Data Fusion Voice/Speech Option
IoT applications increasingly require sensing capabilities that extend beyond what traditional sensors provide.
NPU IP for Data Center and Automotive
The VIP9400 processing family offers programmable, scalable and extendable solutions for markets that demand real time and AI dev…
BCH Encoder and Decoder IP Core
The IP Core implements BCH Code encoding and decoding.
The GenAI IP is the smallest version of our NPU, tailored to small devices such as FPGAs and Adaptive SoCs, where the maximum Fre…
32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification
The L31AS is a 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification.
Neoverse Compute Subsystems N2 (CSS N2)
Neoverse CSS N2: The Arm Neoverse N2 Platform, Delivered to Partners as a Verified, Performance-Validated Customizable Subsystem …
A CPU Foundation for the AI-Driven Datacenter The Arm Neoverse V3 CPU is built to deliver maximum performance for cloud applicati…