Vendor: MVD Cores Category: Video Transport

ASI Receiver

The MVD ASI receiver core is a drop-in module that includes the following functions : • Clock/Data recovery • Serial/parallel Con…

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Overview

The MVD ASI receiver core is a drop-in module that includes the following functions :
• Clock/Data recovery
• Serial/parallel Conversion
• Sync Byte (FC Comma Detection)
• 8B/10B decoding
• Auto adaptation to 188/204 bytes packet Input
• 188 bytes MPEG-TS output
No external components required (1)
(1) External equalizer and/or transformer is recommended for long cable interfaces.

Key features

  • Multi mode ASI receiver
  • • European standard EN50083-9 Annex B
  • • Drop-in module for Virtex-6™, Virtex-5™, Spartan-6™ and Spartan™-3/E/A FPGAs
  • • 27MHz Single Clock
  • • Supports 188 or 204 bytes packet input
  • • Supports direct ASI interface (clock recovery from Data)
  • • Supports Data Packet or Data Burst format
  • • Single channel – support for multi channel
  • • Full synthesizable RTL VHDL design (not delivered) for easy customization
  • • Design delivered as Netlist

Benefits

  • ASI Receiver may be used in applications related to
  • DVB/MPEG-2 transport streams.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
MVD_ASI_RX
Vendor
MVD Cores

Provider

MVD Cores
HQ: France
MVD Cores is an engineering team highly specialized in Digital Video Broadcasting (DVB) and FPGA technologies. We provide IP cores for Processing, Transporting and Transmission of MPEG, DVB, ATSC & IPTV standards for Xilinx FPGAs. The products and services catalog contains a wide range of on-the-shelf IPs to build solutions to carry MPEG-TS to RF. Our IPs cover almost all worldwide standards of current technologies for broadcasting over Digital Terrestrial Television (DTT), Cable TV (CATV) and Satellite.
Contact MVD Cores

Learn more about Video Transport IP core

Enabling High Performance SoCs Through Multi-Die Re-use

This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel between two or more dice.

An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC)

This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed archi­tecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC.

Frequently asked questions about Video Transport IP cores

What is ASI Receiver?

ASI Receiver is a Video Transport IP core from MVD Cores listed on Semi IP Hub.

How should engineers evaluate this Video Transport?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Transport IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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