Band Gap IP, Input: 1.0V - 1.8V, VBG=0.615V, UMC 0.18um LL process
VBG=0.615V, VCCA=1.8V, VCCA_min=1.0V, Ivcca=23uA, UMC 0.18um LL Logic process.
- UMC
- 180nm
- LL
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Band Gap IP, Input: 1.0V - 1.8V, VBG=0.615V, UMC 0.18um LL process
VBG=0.615V, VCCA=1.8V, VCCA_min=1.0V, Ivcca=23uA, UMC 0.18um LL Logic process.
Linear Regulator IP, Output: 3.3V/100mA, UMC 0.15um SP process
3.3V with 100mA driving capability, Istb=65uA Linear Regulator, UMC 0.15um SP Logic process.
D/A Converter IP, 16 bits, 96Ksps, UMC 0.18um G2 process
16-Bit 96KSPS voltage output stereo-line Digital-to-Analog converter, UMC 0.18um GII Logic process.
10-Bit 44MSPS dual channel differential current output Digital-to-Analog converter, UMC 0.18um GII Logic process.
A/D Converter IP, 10 bits, 400Ksps, UMC 0.25um Logic process
10-Bit 400KSPS single-end Analog-to-Digital converter, UMC 0.25um Logic process.
A/D Converter IP, 10 bits, 40Msps, UMC 0.18um Mixed-Mode process
10-Bit 40MSPS Differential Analog-to-Digital converter, UMC 0.18um Mixed-Mode process.
Voltage Detector IP, 3 Levels, UMC 0.18um G2 process
3-level detector for MMC flash storage, VCCA=3.3V, Ivcca=65uA, UMC 0.18um GII Logic process.
Voltage Detector IP, UMC 0.25um Logic process
0.25um process 2 level voltage detector, UMC 0.25um Logic process.
Band Gap IP, Input: 1.2V - 3.3V, VBG=0.615V, UMC 0.18um G2 process
VBG=0.615V, VCCAH=3.3V, VCCAH_min=1.2V, Ivccah=25uA, UMC 0.18um GII Logic process.
Band Gap IP, Input: 1.0V - 1.2V, VBG=0.8V, UMC 0.13um LL/FSG process
VBG=0.8V, VCCA=1.2V, VCCA_min=1.0V, Ivcca=45uA, UMC 0.13um LL Logic/FSG process.
Band Gap IP, Input: 1.0V - 1.5V, VBG=0.615V, UMC 0.15um SP process
VBG=0.615V, VCCA=1.5V, VCCA_min=1.0V, Ivcca=23uA, UMC 0.15um SP Logic process.
Band Gap IP, Input: 2.0V - 3.3V, VBG=1.23V, UMC 0.25um Logic process
VBG=1.23V, VCCAH=3.3V, VCCAH_min=2.0V, Ivccah=25uA, UMC 0.25um Logic process.
Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process
FXPORD730HA0A 0.18um power on reset at the corner of D-type IO Vrr=1.2V Vfr=1V, Power On Reset, UMC 0.18um GII Logic process.
Power on Reset IP, Input: 1.5V, UMC 0.15um SP process
Vrr=1.1V Vfr=0.95V, VCC=1.5V, B-type IO., Power On Reset, UMC 0.15um SP Logic process.
RC Oscillator IP, Output: 12KHz, UMC 0.18um G2 process
sub-low current 12KHz RC-Oscillator, UMC 0.18um GII Logic process.
RC Oscillator IP, Output: 30KHz - 300KHz, UMC 0.25um Logic process
External-C, frequency 30KHz~300KHz, VCCA=2.0V~3.0V, UMC 0.25um Logic process.
Audio ADDA IP, 16 bits, 96KHz, UMC 0.18um G2 process
16-Bit 96KHz Sigma-Delta audio Codec, UMC 0.18um GII Logic process.
A/D Converter IP, 18 bits, 96Ksps, UMC 0.25um Logic process
18-Bit 96KSPS differential Sigma-Delta Analog-to-Digital converter, UMC 0.25um Logic process.
Fully-integrated 4X PLL clock generator
IP
Low-power 8-bit 80 MHz SAR ADC
The data converter IP portfolio includes low-power SAR ADCs, flash ADCs, and high-speed I/Q DACs optimized for RF and baseband pa…