Clocking and timing IP cores are fundamental to semiconductor designs that require accurate clock generation, distribution, synchronization, and timing control. This category includes PLLs, DLLs, oscillators, and clock generators used in SoCs, ASICs, SerDes subsystems, processors, memory interfaces, and communication devices.
Browse clocking and timing IP from multiple vendors to compare jitter, frequency range, locking behavior, power consumption, programmability, and process support. Semi IP Hub helps chip architects and design engineers identify the right timing IP for high-performance and low-power silicon platforms.
PLL IP, Input: 25MHz, Output: 156.25MHz, UMC 40nm LP process
Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency is 25M for Low-Jitter Mode, 156.25M for Ji…
Oscillator IP, Output: 5KHz, UMC 55nm SP process
Output frequency 5KHz.
DLL (All Digital) IP, Input: 5MHz - 70MHz, Output: 5MHz - 70MHz, UMC 40nm LP process
An ADDLL operate at 5MHz~70MHz.Output produce a rising/falling edge delay tuning clock.UMC 40nm LP/RVT Logic process.
DLL (All Digital) IP, Input: 360MHz - 720MHz, Output: 360MHz - 720MHz, UMC 40nm LP process
Input 360M-720MHz, output 360M-720MHz, DLL, Output 0-180 degree Phase adjustment range.
DLL (All Digital) IP, Input: 300MHz - 600MHz, Input: 300MHz - 600MHz, UMC 40nm LP process
An ADDLL operate at 300MHz~600MHz.Output 0-180 degree Phase adjustment range.Delay adjustment resolution
DDR DLL IP, Input: 66MHz - 200MHz, Output: 66MHz - 200MHz, UMC 90nm SP process
Input 66M-200MHz, output 66M-200MHz, DDR DLL, UMC 90nm SP/RVT Low-K Logic process.
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz -200MHz, UMC 0.18um G2 process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.18um GII Logic process.
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.13um HS/FSG process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.13um HS/FSG Logic process.
DDR DLL IP, Input: 100MHz - 150MHz, Output: 100MHz - 150MHz, UMC 0.18um G2 process
Input 100M-150MHz, output 100M-150MHz, DDR DLL, UMC 0.18um GII Logic process.
IP
1.1V, Max frequency 1.5GHz PLL
1.1V, Max frequency 1.5GHz
PLL (Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/FSG process
5GHz SSCG with 25MHz reference clock, UMC 0.11um 20T HS/FSG Logic process.
PLL (Spread Spectrum) IP, 20MHz - 70MHz, UMC 0.18um G2 process
UMC 0.18um GII Logic process 20MHz-70MHz delay-type spread-spectrum clock generator.
Input clock range:10M ~ 1280MHz, output clock range:15.625M ~ 2000MHz wide-range SSCG, UMC 0.11um HS/AE (AL Enhancement) 2T Logic…
PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Enhancement) 2T Logic process.
PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Enhancement) 2T Logic process.
Input 80M-150MHz, output 80M-150MHz, frequency synthesizable PLL, UMC 0.13um Logic EHS/FSG process.
PLL (Frequency Synthesizer) IP, Input: 66MHz - 100MHz, Output: 400MHz - 800MHz, UMC 90nm SP process
Input 66M-100MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 90nm SP Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 90nm LL process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 90nm LL/RVT process.
PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 55nm LP process
Input 25M-66MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 55nm LP/RVT Low-K Logic process.