Learn more about High-Speed IP core
This post provides an in-depth look at the fundamentals of high-speed interconnects, AI/HPC trends (HBM/D2D/CPO), and the three critical requirements of Physical AI: Deterministic Latency, Functional Safety (ISO 26262), and Automotive Reliability (AEC-Q100).
Innosilicon, a leading IP provider, offers a complete PCIe 5.0 solution stack that includes both PHY and controller IPs. Although both layers are crucial to achieving a fully compliant and high-performance PCIe interface, this paper deep dives into the technical challenges of PHY design, highlighting insights drawn from real-world design margins, receiver robustness, and advanced jitter analysis in the context of Gen5 systems.
LTTPR support is quickly becoming a cornerstone of next-gen DisplayPort architectures, particularly in automotive, industrial, and multi-display environments. Here's what you need to know.
Protocol standards and speeds are advancing rapidly to boost productivity and efficiency for high-performance computing (HPC), AI training, and other applications, with the arrival of PCI Express (PCIe) 7.0 being the latest example.
Maximize limited package pins with IO that can act as high-speed test ports then be reused as low-power GPIOs during field operation.
TSMC Symposium took place from April 23, 2025, at Santa Clara Convention Center, USA.
