subLVDS IO Pad Set
The LVDS I/O is a three-module design (input, output and reference block).
Overview
The LVDS I/O is a three-module design (input, output and reference block). The LDP_OU_450_18V_T is a 1400MBit/s LVDS Driver, LDP_IN_450_18V_DN is a 1400MBit/s LVDS Receiver and the LDP_RE_000_18V is the voltage reference and current bias for up to 16 drivers. The LDP_OU_450_18V_T is designed to drive either 50? or 100? differential termination. This cell has been designed to meet the standard SubLVDS specifications (SMIA 1.0 Part 2:CCP2). Currently there is no standard for 50? termination
Using this SubLVDS Pad Set, the system can achieve very high data rates per pin with simple termination requirements and low EMI. The driver has been optimized for speed/power and can be ported to various pure digital CMOS processes from 0.18um down to 28nm technologies. The LDP_OU_450_18V_T has been optimized for 1400MBit/s operations. The receiver has been designed with no hysteresis in order to optimize sensitivity and skew.
The driver design has all the necessary components for transmit of SubLVDS data and a temperature stable internal reference for setting of the SubLVDS signaling voltage and common mode level. This provides user flexibility in deploying multiple SubLVDS transmitters. The reference block is required for the SubLVDS drivers to provide a stable common mode voltage as well as an accurate current reference for the driver source / sink current. Maximum operating frequency is 700 MHz.
Key features
- ? Powered from 1.8V ±10% and 1.1V to 1.2V (±10%) core power supplies
- ? Operates up to 700 MHz (1400Mbps)
- ? Input receive sensitivity of 50mV peak differential (without hysteresis)
- ? Common mode range from 0.4V to 1.4V (limited by Power Supply)
- ? Power-up Sequence Independent
- ? Duty Cycle Distortion (DCD) 50ps typical
- ? Power consumption is 1.8 mW typical and 5 mW maximum
What’s Included?
- Physical abstract in LEF format (.lef)
- Timing models in Synopsys Liberty formats (.lib and .db)
- Calibre compatible LVS netlist in CDL format (.cdl)
- GDSII stream (.gds)
- Behavioral Verilog (.v)
- Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- Databook (.pdf)
- Library User Guide - ESD Guidelines (.pdf)
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| GlobalFoundries | 40nm | 40 400 nm | Silicon Proven |
Specifications
Identity
Provider
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Frequently asked questions about High-Speed I/O Pad IP
What is subLVDS IO Pad Set?
subLVDS IO Pad Set is a High-Speed IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for globalfoundries Silicon Proven.
How should engineers evaluate this High-Speed?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this High-Speed IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.