Vendor: Aragio Solutions Category: High-Speed

ONFI IO Pad Set

The ONFI library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage referen…

GlobalFoundries 40nm Silicon Proven View all specifications

Overview

The ONFI library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage reference cell to support both single-ended and differential ONFI 3.0 signaling. This library also meets the requirements for Toggle 2.0 signaling. The pad set includes a full complement of power, spacer, and adapter cells to assemble a complete pad ring by abutment. An included rail splitter allows isolated ONFI domains to be placed in the same pad ring with other power domains while maintaining continuous VDD/VSS in the pad ring for robust ESD protection.

? ONFI 3.0 Single-Ended Driver /Receiver
? ONFI 3.0 Differential Clock Driver / Receiver
? ODT / ZO Calibration Cell
? Voltage Reference

The ONFI I/O library supports all impedance modes defined in the ONFI 3.0 specification and features fast and precise calibration, low power consumption, area-efficient design, and easy integration into the physical layer (PHY).

Key features

  • ONFI Single-Ended Driver / Receiver Features:
  • ? Driver – user-selectable on-die termination and programmable drive strength with ODT / ZO calibration and programmable “off” state control.
  • o ODT Rtt = 30? / 50? / 75? / 100? / 150?
  • o ZOUT = 18? / 25? / 35? / 50?
  • o Off state – Z / pull-up / pull-down / bus keeper
  • ? Receiver – single-ended and pseudo-differential outputs
  • ? Powered by 1.8V / 3.3V I/O and 1.1V / 1.2V core supplies
  • ? Maximum operating frequency – 200 MHz
  • Differential Clock Driver / Receiver Features:
  • ? Driver – user-selectable on-die termination and programmable drive strength with ODT / ZO calibration and programmable “off” state control.
  • o ODT Rtt = 30? / 50? / 75? / 100? / 150?
  • o ZOUT = 18? / 25? / 35? / 50?
  • o Off state – Z / pull-up / pull-down / bus keeper
  • ? Receiver – single-ended and true differential outputs
  • ? Powered by 1.8V / 3.3V I/O and 1.1V / 1.2V core supplies
  • ? Maximum operating frequency – 200 MHz

What’s Included?

  • Physical abstract in LEF format (.lef)
  • Timing models in Synopsys Liberty formats (.lib and .db)
  • Calibre compatible LVS netlist in CDL format (.cdl)
  • GDSII stream (.gds)
  • Behavioral Verilog (.v)
  • Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • Databook (.pdf)
  • Library User Guide - ESD Guidelines (.pdf)

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 40nm 40 400 nm Silicon Proven

Specifications

Identity

Part Number
RGO_GF40_25V33_LP_30C_ONFI
Vendor
Aragio Solutions

Provider

Aragio Solutions
HQ: USA
Aragio is a limited liability corporation (LLC) with headquarters in Plano, Texas. The Company is a full-service provider of semiconductor intellectual property (IP) for integrated circuit (IC) design. Aragio focuses on design solutions for input/output (I/O) system interface cells used for package interconnect. Full I/O library solutions, with robust electrostatic discharge (ESD) protection, are provided for complex integrated circuit padring designs. Aragio serves a very niche market for I/O libraries within the semiconductor industry. The company provides uniform I/O pad sets for a wide range of applications, semiconductor foundries and technologies. It is significant that all IP is owned by Aragio Solutions and nearly all IP developed since the company was formed in 2003 is still in demand and will continue to be in demand for the next decade. As a recognized world leader, Aragio provides its services to numerous clients across Southeast Asia, China, Japan, Europe, and North America.

Learn more about High-Speed IP core

PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions

Innosilicon, a leading IP provider, offers a complete PCIe 5.0 solution stack that includes both PHY and controller IPs. Although both layers are crucial to achieving a fully compliant and high-performance PCIe interface, this paper deep dives into the technical challenges of PHY design, highlighting insights drawn from real-world design margins, receiver robustness, and advanced jitter analysis in the context of Gen5 systems.

Frequently asked questions about High-Speed I/O Pad IP

What is ONFI IO Pad Set?

ONFI IO Pad Set is a High-Speed IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for globalfoundries Silicon Proven.

How should engineers evaluate this High-Speed?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this High-Speed IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP