Vendor: Aragio Solutions Category: High-Speed

LVDS IO Pad Set

The LVDS I/O is a three-module design (input, output and reference block).

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GlobalFoundries 40nm Silicon Proven View all specifications

Overview

The LVDS I/O is a three-module design (input, output and reference block). The LDP_OU_675_25V_T is a 2GBit/s LVDS Driver, LDP_IN_675_25V_DN is a 2GBit/s LVDS Receiver and the LDP_RE_000_25V is the voltage reference for up to 16 drivers. The LDP_OU_675_25V_T is designed to drive either 50? or 100? differential termination. This cell has been designed to meet a set of the standard LVDS specifications (IEEE Std 1596.3-1996, Low Voltage Differential Signaling).

Using this LVDS Pad Set, the system can achieve very high data rates per pin with simple termination requirements and low EMI. Both driver and receiver have been optimized for speed/power and can be ported to various pure digital CMOS processes from 0.18um down to 28nm technologies. The LDP_OU_675_25V_T has been optimized for 2GBit/s operations. The receiver has been designed with no hysteresis in order to optimize sensitivity and skew.

The driver design has all the necessary components for transmit of LVDS data and a temperature stable internal reference for setting of the LVDS signaling voltage and common mode level. This provides user flexibility in deploying multiple LVDS transmitters. The reference block is required for the LVDS drivers to provide a stable common mode voltage as well as an accurate current reference for the driver source / sink current. Maximum operating frequency is 1GHz.

Key features

  • Powered from 2.5V ±10% and 1.1V to 1.2V (±10%) core power supplies
  • ? Operates up to 1GHz (2Gbps)
  • ? Input receive sensitivity of 75mV peak differential (without hysteresis)
  • ? Common mode range from 0V to 2.4V (limited by Power Supply)
  • ? Power-up sequence independent
  • ? Power consumption is 5 mW typical and 7.5 mW maximum at 1GHz

What’s Included?

  • Physical abstract in LEF format (.lef)
  • Timing models in Synopsys Liberty formats (.lib and .db)
  • Calibre compatible LVS netlist in CDL format (.cdl)
  • GDSII stream (.gds)
  • Behavioral Verilog (.v)
  • Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • Databook (.pdf)
  • Library User Guide - ESD Guidelines (.pdf)

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 40nm 40 400 nm Silicon Proven

Specifications

Identity

Part Number
RGO_GF40_25V25_LP_UC_LVDS
Vendor
Aragio Solutions

Provider

Aragio Solutions
HQ: USA
Aragio is a limited liability corporation (LLC) with headquarters in Plano, Texas. The Company is a full-service provider of semiconductor intellectual property (IP) for integrated circuit (IC) design. Aragio focuses on design solutions for input/output (I/O) system interface cells used for package interconnect. Full I/O library solutions, with robust electrostatic discharge (ESD) protection, are provided for complex integrated circuit padring designs. Aragio serves a very niche market for I/O libraries within the semiconductor industry. The company provides uniform I/O pad sets for a wide range of applications, semiconductor foundries and technologies. It is significant that all IP is owned by Aragio Solutions and nearly all IP developed since the company was formed in 2003 is still in demand and will continue to be in demand for the next decade. As a recognized world leader, Aragio provides its services to numerous clients across Southeast Asia, China, Japan, Europe, and North America.
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Frequently asked questions about High-Speed I/O Pad IP

What is LVDS IO Pad Set?

LVDS IO Pad Set is a High-Speed IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for globalfoundries Silicon Proven.

How should engineers evaluate this High-Speed?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this High-Speed IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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