Vendor: NTLab Category: Single-Protocol PHY

1 Gbps Rail to Rail LVDS receiver

065TSMC_LVDS_08 is LVDS receiver with rail to rail input range.

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TSMC 65nm GP Silicon Proven View all specifications

Overview

065TSMC_LVDS_08 is LVDS receiver with rail to rail input range. The interface to the core logic includes the output signal pins (OUTP, OUTN) to receive data and the control pin EN_RX to configure the state of the receiver. The VREF12 pin is input voltage reference. Pin IREF_RX to get current reference from receiver bias. PAD_INP and PAD_INN are complementary input to connect to the bonding pads. This LVDS receiver does not employ hysteresis, and therefore does not comply with the hysteresis requirement of the TIA and IEEE standards for LVDS differential signaling at the specified rates.

Key features

  • TSMC CMOS 0.065 um
  • 2.5 V analog power supply
  • 1.2 V digital power supply
  • 1.2 V CMOS input and output logic signals
  • 1 Gbps (DDR MODE) switching rates
  • Conforms to TIA/EIA-644 LVDS standards without hysteresis
  • Rail to rail input range
  • Temperature range: -40 °C to + 125 °C
  • Optimized for pad-limited layout design
  • Portable to other technologies (upon request)

Block Diagram

065TSMC_LVDS_08 block diagram

Applications

  • Point-to-point data receiver
  • Multidrop buses
  • Clock distribution
  • Backplane receiver
  • Backplane data receiver
  • Cable data receiver

What’s Included?

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 65nm GP Silicon Proven

Specifications

Identity

Part Number
065TSMC_LVDS_08
Vendor
NTLab

Provider

NTLab
HQ: Lithuania
NTLab is a vertically integrated microelectronics design center. It has 70+ experienced and qualified engineers. NTLab specializes in the designing of mixed-signal and RF ICs and Systems-on-Chip. It has a wide range of own silicon-verified IP blocks: processor cores, interfaces, analog and high-frequency PHYs, etc., thus allowing customized design to be fast and predictable. In-company unique combination of competences in digital, analog and RF circuits and embedded software enables NTLab to participate in the projects that require deep research and utilize most sophisticated and advanced techniques: multi-system GPS/GLONASS/Galileo/BeiDou/NavIC(IRNSS)/QZSS/SBAS navigation, RF ID, wireless communications, etc. All designed ICs are provided with test and development tools, as well as with reference software. NTLab offers a wide range of silicon proven analog/mixed-signal IPs in 0.35µm, 0.25 µm, 0.18 µm, 0.13 µm, 0.09 µm, 65nm, 55nm, 40nm, 28nm, 22 nm CMOS and SiGe BiCMOS processes. These IPs are suitable for devices targeted both consumer and industrial markets. Most of these IPs have been proven in silicon on the foundries: Samsung, UMC, GlobalFoundries, SMIC, VIS, Tower, X-FAB, iHP, AMS, SilTerra, STMicroelectronics, Winfoundry.
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Frequently asked questions about Single-Protocol PHY IP

What is 1 Gbps Rail to Rail LVDS receiver?

1 Gbps Rail to Rail LVDS receiver is a Single-Protocol PHY IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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