Vendor: Noesis Technologies Category: Single-Protocol PHY

Clock and Data Recovery of HDB3/B3ZS coded signals

An all-digital solution suitable for clock/data recovery of HDB3/B3ZS coded signals.

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TSMC 180nm BCDG2 Silicon Proven View all specifications

Overview

An all-digital solution suitable for clock/data recovery of HDB3/B3ZS coded signals.

Key features

  • Performs receive clock and data recovery on HDB3/B3ZS coded data.
  • Programmable jitter attenuator.
  • Loss of signal detection.
  • Frequency aided acquisition using external reference clock.
  • Fast acquisition time.
  • Narrow bandwidth digital phase locked Loop.
  • NCO used for an all-digital implementation.

Block Diagram

ntCDR block diagram

What’s Included?

  • Synthesizable VHDL or Verilog source code.
  • VHDL or Verilog test bench with example configuration files.
  • Synthesis scripts.
  • Users manual.
  • Free 3 months technical support.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 180nm BCDG2 Silicon Proven

Specifications

Identity

Part Number
ntCDR
Vendor
Noesis Technologies

Provider

Noesis Technologies
HQ: Greece
Noesis Technologies specializes in design,development and marketing of high quality, cost effective communication IP cores and provides expert ASIC/FPGA design services in telecom DSP area. Our solutions are key components to the most sophisticated telecom systems. Backed-up by our leading-edge expertise on forward error correction, encryption and networking technology as well as on DSP algorithm development we provide robust solutions that are used to improve data quality, increase bandwidth or reduce the overall system cost of end-application.
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Learn more about Single-Protocol PHY IP core

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Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is Clock and Data Recovery of HDB3/B3ZS coded signals?

Clock and Data Recovery of HDB3/B3ZS coded signals is a Single-Protocol PHY IP core from Noesis Technologies listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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