High-Performance DSPs -> Serial interconnects back high-performance computing
Serial interconnects back high-performance computing
By Steve Paavola, Director of Advanced Development, Sky Computers Inc., Chelmsford, Mass., EE Times
January 4, 2002 (7:23 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011115S0062
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related White Papers
- Optimizing High Performance CPUs, GPUs and DSPs? Use logic and memory IP - Part II
- Improving Design Timing and Simplicity for Lower Cost and High Performance Multistandard Audio Decoder STA012
- Processor Architecture for High Performance Video Decode
- NetComposer-II: High performance Structured ASIC Programmable NPU platform for layer 4-7 applications
Latest White Papers
- RISC-V basics: The truth about custom extensions
- Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
- Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
- relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions