High-Performance DSPs -> Serial interconnects back high-performance computing
Serial interconnects back high-performance computing
By Steve Paavola, Director of Advanced Development, Sky Computers Inc., Chelmsford, Mass., EE Times
January 4, 2002 (7:23 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011115S0062
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 10-bit Pipeline ADC - Tower 180 nm
- NoC Verification IP
- Simulation VIP for Ethernet UEC
- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
Related Articles
- Optimizing High Performance CPUs, GPUs and DSPs? Use logic and memory IP - Part II
- Processor Architecture for High Performance Video Decode
- NetComposer-II: High performance Structured ASIC Programmable NPU platform for layer 4-7 applications
- Multi-Gigabit SerDes: The Cornerstone of High Speed Serial Interconnects
Latest Articles
- Analog Foundation Models
- Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators
- RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI
- Exclude Smart in Functional Coverage
- A 0.32 mm² 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection