TSMC 3-nm Upgrade in Japan to Catch up With Demand
By Alan Patterson, EE Times | February 10, 2026

TSMC’s plan to upgrade its existing facilities in Japan to 3-nm node is aimed at catching up with strong AI demand in both domestic and global markets, analysts told EE Times.
TSMC CEO C.C. Wei announced the decision during a televised meeting with Japanese Prime Minister Sanae Takaichi. The foundry will transfer its 3-nm manufacturing process technology to its second fab near the southern city of Kumamoto, which was originally designed to produce 6-nm chips.
TSMC is upgrading in Japan as the company struggles to keep pace with demand. The company has budgeted a record $52 to $56 billion for capital expenditures this year, an increase of as much as 37% compared with 2025. TSMC hinted that it will continue to ramp up investment over the next three years. While the company didn’t disclose the size of the planned investment in Japan, analysts who spoke to EE Times estimated the value of the upgrade to be as much as $20 billion.
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