SoC-e Announces New Release of Managed Ethernet Switch (MES) IP Core Supporting DLR for Ethernet/IP
January 24, 2018 -- Device Level Ring (DLR) is a Layer-2 protocol that provides media redundancy in a ring topology. The DLR protocol is intended primarily for implementation in Ethernet/IP end-devices that have two Ethernet ports and embedded switch technology. The DLR protocol provides fast network fault detection and reconfiguration in order to support the most demanding control applications.
A DLR network includes at least one node configured to be a Ring Supervisor, and any number of Beacon Based Nodes. It is assumed that all the ring nodes have at least two Ethernet ports and incorporate embedded switch technology.
The new realease of SoC-e’s MES IP Core (Managed Ethernet Switch) fully supports DLR protocol. The IP Core allows to implement a DLR end-device, with embedded switching capabilities and supports multiple Ethernet interfaces. The following network node configurations can be implemented with the MES IP Core:
- Ring Supervisor Node
- Beacon Based Node
Related Semiconductor IP
Related News
- SoC-e's Managed Ethernet Switch now supports up-to 32 ports
- Fraunhofer IPMS develops new 10G TSN endpoint IP Core for deterministic high-speed Ethernet networks
- CAST Introduces MAC-SEC-MG IP Core for Secure 10G+ Ethernet SoC Designs
- Comcores provide Flexible Ethernet Switch IP Design Optimized for switching in C-RAN and Next-Generation LTE Advanced Networking Equipment
Latest News
- VeriSilicon Drives Commercial Adoption of AV2 Across Next-Generation Video and Streaming Applications
- Cadence Announces Collaboration with Intel Foundry to Accelerate Intel 14A Process Optimization for HPC and Mobile Designs
- Menta and Presto Engineering Announce Strategic Collaboration to Accelerate Adaptive ASIC Architectures with Embedded FPGA Technology
- MIPI A-PHY To Power Industry’s First Four-Company Automotive SerDes Interoperability Demonstration at AutoSens USA
- Altera Introduces Next-Generation Agilex 9 Direct RF-Series SoC FPGA to Power the Future of High-Performance RF Systems