MorethanIP releases the first combined 10GBase-R/W Core for 10 Gigabit Ethernet LAN and WAN PHY applications for FPGA
Karlsfeld August 14, 2003 - MorethanIP completes its 10G Ethernet offering, releasing the first combined 10GBase-R/W Core for 10 Gigabit Ethernet LAN and WAN PHY applications for FPGA. The 10GBase-R/W PHY combines the MorethanIP proven 10 Gigabit PCS (Physical Coding Sub-Layer) Core with Altera's OC-192 SONET Megacore in a single integrated solution for Altera Stratix devices and lower cost Hardcopy masked solutions.
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
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