Flex Logix Announces Reconfigurable Block RAM with ECC Option

EFLX is the Only eFPGA with Automatic Flexible Hardware Error Correction

MOUNTAIN VIEW, Calif. – September 18, 2023 – Flex Logix® Technologies, Inc., the leading supplier of eFPGA IP, announced today the availability of Reconfigurable Block RAM with ECC and Parity Options.

“Our customers want Block RAM (BRAM) that is flexible. The majority of customer designs use BRAM. But they have different requirements. Some want deep memory with a 16-bit data path width. Others want very wide data path widths. BRAM access can be configured for single port or two port or true dual port,” said Geoff Tate, CEO of Flex Logix. “Many applications also want a level of data checking for soft errors. Some want parity and others want full Error Detection and Correction. In the past they had to implement these features in Verilog adding complexity and using LUTs, or requesting customization from us at the cost of time and money. Now we have a single Reconfigurable Block RAM that can meet all of these needs.”

The Reconfigurable BRAM is available now for Generation 2.4 EFLX eFPGA designs in multiple popular process nodes.

About Flex Logix

Flex Logix is a reconfigurable computing company providing leading edge eFPGA and AI Inference technologies for semiconductor and systems companies. Flex Logix eFPGA enables volume FPGA users to integrate the FPGA into their companion SoC, resulting in a 5-10x reduction in the cost and power of the FPGA and increasing compute density which is critical for communications, networking, data centers, microcontrollers and others. Its scalable AI inference is the most efficient, providing much higher inference throughput per square millimeter and per watt. Flex Logix supports process nodes from 180nm to 7nm, with 5nm and 3nm in development. Flex Logix is headquartered in Mountain View, California and has an office in Austin, Texas. For more information, visit https://flex-logix.com.